Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

On-Chip Power Supply Noise: Scaling, Suppression and Detection

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed

A design methodology for robust, energy-efficient, application-aware memory systems

Memory design is a crucial component of VLSI system design from area, power and performance perspectives. To meet the increasingly challenging system specifications, architecture, circuit and device level innovations are required for existing memory technologies. Emerging memory solutions are widely explored to cater to strict budgets. This thesis presents design methodologies for custom memory design with the objective of power-performance benefits across specific applications. Taking example of STTRAM (spin transfer torque random access memory) as an emerging memory candidate, the design space is explored to find optimal energy design solution. A thorough thermal reliability study is performed to estimate detection reliability challenges and circuit solutions are proposed to ensure reliable operation. Adoption of the application-specific optimal energy solution is shown to yield considerable energy benefits in a read-heavy application called MBC (memory based computing). Circuit level customizations are studied for the volatile SRAM (static random access memory) memory, which will provide improved energy-delay product (EDP) for the same MBC application. Memory design has to be aware of upcoming challenges from not only the application nature but also from the packaging front. Taking 3D die-folding as an example, SRAM performance shift under die-folding is illustrated. Overall the thesis demonstrates how knowledge of the system and packaging can help in achieving power efficient and high performance memory design.Ph.D

In situ Manipulation of Magnetization via Direct Mechanical Interaction in Magnetostrictive Thin Films

The pursuit of a universal memory- possessing fast write/read times, nonvolatile and unlimited data endurance, low operating power, low manufacture costs, high bit density, as well as being easily integrable with on-trend complementary metal-oxide semiconductor (CMOS) devices- has reenergized research in the field of multiferroic and magnetoelectric materials. Such materials simultaneously exhibit ferroelectricity and ferromagnetism, and allow for the coupling of the two order parameters, known as magnetoelectric coupling. This coupling is enhanced in magnetostrictive/piezoelectric bilayer systems where applied electrical bias can modify magnetic order via strain-mediation, a mechanism that can reduce the power demands in emerging magnetic random access memory (MRAM) technologies. We have previously investigated this relationship in an Fe0.7Ga0.3/BaTiO3 bilayer structure using magnetic contrast imaging techniques with in situ applied electric fields. The goal of this thesis was to explore methods to better control magnetoelectric effects in order to enhance local magnetic response to external stimuli. Specifically, we investigated magnetoelastic response of freestanding, magnetostrictive Fe0.7Ga0.3 thin films via direct mechanical interaction with an external probe, as the well known strain-mediated mechanism in magnetoelectric devices depends on the lesser known magnetoelastic nature of strain transfer between the distinct material phases. Magnetoelastic effects are directly associated with both external magnetic field and stress via Lorentz-force transmission electron microscopy (LTEM) contrast techniques, and the hysteresis of magnetic order was charted with respect to both stimuli. For relevant application to MRAM devices, we have initiated studying these effects in patterned media as well, where individual, nanoscale magnetic geometries represent bistable bits for memory. We demonstrate static pure stress effects on the magnetoelastic response in continuous thin films, as well as real-time mechanical "writing" of stable domain states. The external probe is directed into the film, inducing a non-uniform, radially symmetric local strain. Micromagnetic simulation reveals that the strength of observed magnetoelastic effects is offset by small, undulating variations in magnetization characteristic of polycrystalline thin films, known as magnetization ripple. Imposing a threshold function on the effective anisotropy of the film describes the spontaneous onset of these effects and the differences in magnetic order for films with hysteresis solely due to stress, or with both field and stress. Thus, a method to achieve bistable logic for MRAM applications using direct uniform stress, in lieu of external fields, is proposed

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

1996 Laboratory directed research and development annual report

This report summarizes progress from the Laboratory Directed Research and Development (LDRD) program during fiscal year 1996. In addition to a programmatic and financial overview, the report includes progress reports from 259 individual R&D projects in seventeen categories. The general areas of research include: engineered processes and materials; computational and information sciences; microelectronics and photonics; engineering sciences; pulsed power; advanced manufacturing technologies; biomedical engineering; energy and environmental science and technology; advanced information technologies; counterproliferation; advanced transportation; national security technology; electronics technologies; idea exploration and exploitation; production; and science at the interfaces - engineering with atoms

Space Station Systems: a Bibliography with Indexes (Supplement 8)

This bibliography lists 950 reports, articles, and other documents introduced into the NASA scientific and technical information system between July 1, 1989 and December 31, 1989. Its purpose is to provide helpful information to researchers, designers and managers engaged in Space Station technology development and mission design. Coverage includes documents that define major systems and subsystems related to structures and dynamic control, electronics and power supplies, propulsion, and payload integration. In addition, orbital construction methods, servicing and support requirements, procedures and operations, and missions for the current and future Space Station are included