On-board processing satellite network architecture and control study

The market for telecommunications services needs to be segmented into user classes having similar transmission requirements and hence similar network architectures. Use of the following transmission architecture was considered: satellite switched TDMA; TDMA up, TDM down; scanning (hopping) beam TDMA; FDMA up, TDM down; satellite switched MF/TDMA; and switching Hub earth stations with double hop transmission. A candidate network architecture will be selected that: comprises multiple access subnetworks optimized for each user; interconnects the subnetworks by means of a baseband processor; and optimizes the marriage of interconnection and access techniques. An overall network control architecture will be provided that will serve the needs of the baseband and satellite switched RF interconnected subnetworks. The results of the studies shall be used to identify elements of network architecture and control that require the greatest degree of technology development to realize an operational system. This will be specified in terms of: requirements of the enabling technology; difference from the current available technology; and estimate of the development requirements needed to achieve an operational system. The results obtained for each of these tasks are presented

NASA SpaceCube Next-Generation Artificial-Intelligence Computing for STP-H9-SCENIC on ISS

Recently, Artificial Intelligence (AI) and Machine Learning (ML) capabilities have seen an exponential increase in interest from academia and industry that can be a disruptive, transformative development for future missions. Specifically, AI/ML concepts for edge computing can be integrated into future missions for autonomous operation, constellation missions, and onboard data analysis. However, using commercial AI software frameworks onboard spacecraft is challenging because traditional radiation-hardened processors and common spacecraft processors cannot provide the necessary onboard processing capability to effectively deploy complex AI models. Advantageously, embedded AI microchips being developed for the mobile market demonstrate remarkable capability and follow similar size, weight, and power constraints that could be imposed on a space-based system. Unfortunately, many of these devices have not been qualified for use in space. Therefore, Space Test Program - Houston 9 - SpaceCube Edge-Node Intelligent Collaboration (STP-H9-SCENIC) will demonstrate inflight, cutting-edge AI applications on multiple space-based devices for next-generation onboard intelligence. SCENIC will characterize several embedded AI devices in a relevant space environment and will provide NASA and DoD with flight heritage data and lessons learned for developers seeking to enable AI/ML on future missions. Finally, SCENIC also includes new CubeSat form-factor GPS and SDR cards for guidance and navigation

Software Defined Radio Architecture Contributions to Next Generation Space Communications

Space communications architecture concepts, comprising the elements of the system, the interactions among them, and the principles that govern their development, are essential factors in developing National Aeronautics and Space Administration (NASA) future exploration and science missions. Accordingly, vital architectural attributes encompass flexibility, the extensibility to insert future capabilities, and to enable evolution to provide interoperability with other current and future systems. Space communications architectures and technologies for this century must satisfy a growing set of requirements, including those for Earth sensing, collaborative observation missions, robotic scientific missions, human missions for exploration of the Moon and Mars where surface activities require supporting communications, and in-space observatories for observing the earth, as well as other star systems and the universe. An advanced, integrated, communications infrastructure will enable the reliable, multipoint, high-data-rate capabilities needed on demand to provide continuous, maximum coverage for areas of concentrated activity. Importantly, the cost/value proposition of the future architecture must be an integral part of its design; an affordable and sustainable architecture is indispensable within anticipated future budget environments. Effective architecture design informs decision makers with insight into the capabilities needed to efficiently satisfy the demanding space-communication requirements of future missions and formulate appropriate requirements. A driving requirement for the architecture is the extensibility to address new requirements and provide low-cost on-ramps for new capabilities insertion, ensuring graceful growth as new functionality and new technologies are infused into the network infrastructure. In addition to extensibility, another key architectural attribute of the space communication equipment's interoperability with other NASA communications systems, as well as those communications and navigation systems operated by international space agencies and civilian and government agencies. In this paper, we review the philosophies, technologies, architectural attributes, mission services, and communications capabilities that form the structure of candidate next-generation integrated communication architectures for space communications and navigation. A key area that this paper explores is from the development and operation of the software defined radio for the NASA Space Communications and Navigation (SCaN) Testbed currently on the International Space Station (ISS). Evaluating the lessons learned from development and operation feed back into the communications architecture. Leveraging the reconfigurability provides a change in the way that operations are done and must be considered. Quantifying the impact on the NASA Space Telecommunications Radio System (STRS) software defined radio architecture provides feedback to keep the standard useful and up to date. NASA is not the only customer of these radios. Software defined radios are developed for other applications, and taking advantage of these developments promotes an architecture that is cost effective and sustainable. Developments in the following areas such as an updated operating environment, higher data rates, networking and security can be leveraged. The ability to sustain an architecture that uses radios for multiple markets can lower costs and keep new technology infused

A HIGHLY RELIABLE NON-VOLATILE FILE SYSTEM FOR SMALL SATELLITES

Recent Advancements in Solid State Memories have resulted in packing several Giga Bytes (GB) of memory into tiny postage stamp size Memory Cards. Of late, Secure Digital (SD) cards have become a de-facto standard for all portable handheld devices. They have found growing presence in almost all embedded applications, where huge volumes of data need to be handled and stored. For the very same reason SD cards are being widely used in space applications also. Using these SD Cards in space applications requires robust radiation hardened SD cards and Highly Reliable Fault Tolerant File Systems to handle them. The present work is focused on developing a Highly Reliable Fault Tolerant SD card based FAT16 File System for space applications

A One Chip Hardened Solution for High Speed SpaceWire System Implementations. Session: Components

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASIC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a router with 4 SpaceWire ports and two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, and a memory controller for additional external memory use. The SpaceWire cores are also reused in other ASICs under development. The SpaceWire ASIC is planned for use on the Geostationary Operational Environmental Satellites (GOES)-R, the Lunar Reconnaissance Orbiter (LRO) and other missions. Engineering and flight parts have been delivered to programs and users. This paper reviews the SpaceWire protocol and those elements of it that have been built into the current and next SpaceWire reusable cores and features within the core that go beyond the current standard and can be enabled or disabled by the user. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be reviewed and highlighted. Optional configurations within user systems and test boards will be shown. The physical implementation of the design will be described and test results from the hardware will be discussed. Application of this ASIC and other ASICs containing the SpaceWire cores and embedded microcontroller to Plug and Play and reconfigurable implementations will be described. Finally, the BAE Systems roadmap for SpaceWire developments will be updated, including some products already in design as well as longer term plans

Elektroonika projekteerimine ja testimine ESTCube-2 pardaarvutile koos asendimääramise sensoritega

ESTCube-2 will be a 3U picosatellite planned to launch in 2019 to perform experiments in low Earth orbit. On-board computer system is required to control the satellite while powered up and has to provide computational power and reliable storage for other subsystems. Attitude and orbit control system is responsible for satellite’s detumbling, pointing, spin-up and for controlling thrusters. This thesis presents a prototype electronics board developed for both systems. On-board computer system features STMicroelectronics Cortex-M7 microcontroller with common bus interfaces and point-to-point signaling lines for all other systems planned for ESTCube-2. Data and programs are stored in three types of external non-volatile memories - QSPI NOR flash, FRAM and MRAM. For attitude determination sensors a dedicated connector and a demonstration prototype expansion board were developed featuring magnetometer, accelerometer and two gyroscopes. To test the developed boards simple firmware was written using manufacturer’s provided hardware abstraction layer and an initialization source code generator

Development of a Space Computer - A Low Risk Approach to Control and Data Processing Applications in Small Satellites

In early 1991, Honeywell delivered three RH-1 750A based flight computers to complete the AST III program in support of a Phillips Laboratory Autonomous Navigation Demonstration Satellite. The delivery was significant for the following reasons: it was the first delivery of a space qualified RH-1750A computer, the RH-1750 Multi-Chip Module (MCM) was transitioned from a research and development effort to a B-level flight part, and, design to delivery of the first flight unit was accomplished in only 16 months. The AST III program consists of several sequential efforts which will demonstrate and validate state-of-the-art spacecraft autonomy hardware and software in an operational space environment. The Honeywell 1750A GVSC Flight Computer (GFC), developed for the Air Force\u27s Phillips Lab, achieved its primary goal: develop a low-cost, low-risk computer for onboard data processing while demonstrating a secondary goal of transitioning new technologies to flight in a short period of time. The 1750A CPU utilizes the Honeywell RH-1750 Generic VHSIC Spaceborne Computer (GVSC) chipset. The RH-1750 was developed by Honeywell under an Air Force contract and is manufactured using Honeywell\u27s Radiation Insensitive CMOS (RICMOS)TM III process. The GFC is ideally suited for the small satellite environment. Its low cost, low weight, low power, high performance and flexibility make it an excellent candidate for control and data processing applications. The 32- bit GVSC local bus supports zero wait state access to the static RAM resulting in a maximum throughput of 2.5 MIPS under worst-case conditions. The local expansion bus (also 32 bits), accepts up to four I/O assemblies, including DMA capability, and supports I/O throughput rates up to 2 Mwords per second

Communication Subsystems for Satellite Design

The objective of this chapter is to provide a comprehensive end-to-end overview of existing communication subsystems residing on both the satellite bus and payloads. These subsystems include command and mission data handling, telemetry and tracking, and the antenna payloads for both command, telemetry and mission data. The function of each subsystem and the relationships to the others will be described in detail. In addition, the recent application of software defined radio (SDR) to advanced satellite communication system design will be looked at with applications to satellite development, and the impacts on how SDR will affect future satellite missions are briefly discussed

Advanced space communications architecture study. Volume 2: Technical report

The technical feasibility and economic viability of satellite system architectures that are suitable for customer premise service (CPS) communications are investigated. System evaluation is performed at 30/20 GHz (Ka-band); however, the system architectures examined are equally applicable to 14/11 GHz (Ku-band). Emphasis is placed on systems that permit low-cost user terminals. Frequency division multiple access (FDMA) is used on the uplink, with typically 10,000 simultaneous accesses per satellite, each of 64 kbps. Bulk demodulators onboard the satellite, in combination with a baseband multiplexer, convert the many narrowband uplink signals into a small number of wideband data streams for downlink transmission. Single-hop network interconnectivity is accomplished via downlink scanning beams. Each satellite is estimated to weigh 5600 lb and consume 6850W of power; the corresponding payload totals are 1000 lb and 5000 W. Nonrecurring satellite cost is estimated at $110 million, with the first-unit cost at$113 million. In large quantities, the user terminal cost estimate is $25,000. For an assumed traffic profile, the required system revenue has been computed as a function of the internal rate of return (IRR) on invested capital. The equivalent user charge per-minute of 64-kbps channel service has also been determined

Raven: An On-Orbit Relative Navigation Demonstration Using International Space Station Visiting Vehicles

Since the last Hubble Servicing Mission five years ago, the Satellite Servicing Capabilities Office (SSCO) at the NASA Goddard Space Flight Center (GSFC) has been focusing on maturing the technologies necessary to robotically service orbiting legacy assets-spacecraft not necessarily designed for in-flight service. Raven, SSCO's next orbital experiment to the International Space Station (ISS), is a real-time autonomous non-cooperative relative navigation system that will mature the estimation algorithms required for rendezvous and proximity operations for a satellite-servicing mission. Raven will fly as a hosted payload as part of the Space Test Program's STP-H5 mission, which will be mounted on an external ExPRESS Logistics Carrier (ELC) and will image the many visiting vehicles arriving and departing from the ISS as targets for observation. Raven will host multiple sensors: a visible camera with a variable field of view lens, a long-wave infrared camera, and a short-wave flash lidar. This sensor suite can be pointed via a two-axis gimbal to provide a wide field of regard to track the visiting vehicles as they make their approach. Various real-time vision processing algorithms will produce range, bearing, and six degree of freedom pose measurements that will be processed in a relative navigation filter to produce an optimal relative state estimate. In this overview paper, we will cover top-level requirements, experimental concept of operations, system design, and the status of Raven integration and test activities