Desenvolvimento de técnicas de tolerância à falhas para componentes programáveis por SRAM

Este artigo discute técnicas de tolerância à falhas para componentes programáveis, conhecidos por FPGAs (Field Programmable Cate Arrays). Essas técnicas baseiam-se em modificações a nível de circuito lógico implementadas em descrição de alto nível, sem modificação na arquitetura do FPGA. O método baseado em descrição de alto nível utiliza redundância tripla de módulos (TMR) e a combinação entre redundância dupla de módulos (DMR) com detecção de erros concorrentes (CED), que pode lidar com falhas na parte lógica combinacional e seqüencial. Os métodos foram validados por experimentos ele injeção de falhas emulados em uma placa de prototipação. Os resultados foram analisados em termos de confiabilidade, número de pinos de entrada e saída, área e desempenho.This paper discusses fault-tolerant techniques for programmable devices, the well-know FPGAs (Field Programmable Gate Arrays). These techniques can be based on circuit level modifications, implemented at the high-level description, without modification in the FPGA architecture. The high-level method is based on Triple Modular Redundancy (TMR) and a combination of Duplication Modular Redundancy (DMR) with Concurrent Error Detection (CED) techniques, which are able to cope with upsets in the combinational and in the sequential logic. The methodology was validated by fault injection experiments in an emulation board. Results have been analyzed in terms of reliability, input and output pin count, area and performance

Improvised Reliability Tool for Fault Tolerance Computation

As a size of CMOS transistors in electronic circuits reduced, certainly, the reliability of circuit will decrease as well. Therefore, during designing stage measuring reliability becomes important subject as it will save time and cost of manufacturing. In current literature several reliability models are available. From these models Probabilistic Transfer Matrix (PTM) model gives results more quicker and more accurate compare to others. But these tools measures circuit reliability on manual basis. This project aims to generalize PTM model by creating a tool using Matlab programming language that will measure reliability on Auto-basis. For circuits reliability computation user need to provide netlist of circuit in the form of Gate Sequence Matrix (GSM), Circuit Specification Matrix (CSM) and Gate Location Matrix (GLM). Number of inputs, number of outputs, types of logic gates, their interconnection and layout of logic gates in the circuit described in the netlist of circuit. Reliability tool measures circuit performance in a short period of time compare to conventional manual calculations. Several benchmark test circuits such as C17, Full Adder and 2-4 Decoder simulated in order to calculate reliability of the circuit

Improvised Reliability Tool for Fault Tolerance Computation

As a size of CMOS transistors in electronic circuits reduced, certainly, the reliability of circuit will decrease as well. Therefore, during designing stage measuring reliability becomes important subject as it will save time and cost of manufacturing. In current literature several reliability models are available. From these models Probabilistic Transfer Matrix (PTM) model gives results more quicker and more accurate compare to others. But these tools measures circuit reliability on manual basis. This project aims to generalize PTM model by creating a tool using Matlab programming language that will measure reliability on Auto-basis. For circuits reliability computation user need to provide netlist of circuit in the form of Gate Sequence Matrix (GSM), Circuit Specification Matrix (CSM) and Gate Location Matrix (GLM). Number of inputs, number of outputs, types of logic gates, their interconnection and layout of logic gates in the circuit described in the netlist of circuit. Reliability tool measures circuit performance in a short period of time compare to conventional manual calculations. Several benchmark test circuits such as C17, Full Adder and 2-4 Decoder simulated in order to calculate reliability of the circuit

New methods for evaluating the impact of single event transients in VDSM ICs

ISBN: 0769518311This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach

Synthesis for circuit reliability

textElectrical and Computer Engineerin