High-Speed and Energy-Efficient Ring-Oscillator for Analog-to-Digital Conversion

The aim of this conference is to offer the possibility to present and discuss new research results on the area of integrated circuits and systems and all its fields of application. A major emphasis has been given in the technical program to emerging topics such as electronic systems for artificial intelligence, reliability of circuits and devices, unconventional computing, smart sensors and other relevant topics. The conference on Design of Circuits and Integrated Systems (DCIS) is an international meeting for researchers in the highly active fields of micro- and nano-electronic circuits and integrated systems. It provides an excellent forum to present and discuss works on the emerging challenges offered by technology, in the areas of modeling, design, implementation and test of devices, circuits and systems. The 35th edition will be organized by Universidad Politécnica de Madrid

デジタル チョサクケン ホゴ ノ タメ ノ オンセイ シゴウ ノ コウソク アンゴウカ シ ュホウ ニ カンスル ケキュウ

This paper is based on “Partial Encryption Method That Enhances MP3 Security” , by the same authors, which appeared in the Proceedings of 2014 IEEE Asia Pacific Conference on Circuits and Systems, Copyright(C)2014 IEICE. The material in this paper was presented in part at the Proceedings of 2014 IEEE Asia Pacific Conference on Circuits and Systems, and all the figures of this paper are reused form under the permission of the IEICE.© 2014 IEEE. Reprinted, with permission, from T. T. Oo and T. Onoye, "Progressive audio scrambling via wavelet transform," 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Ishigaki, 2014, pp. 97-100. doi: 10.1109/APCCAS.2014.7032728© 2014 IEEE. Reprinted, with permission, from T. T. Oo and T. Onoye, "Progressive audio scrambling via complete binary tree's traversal and wavelet transform," Signal and Information Processing Association Annual Summit and Conference (APSIPA), 2014 Asia-Pacific, Siem Reap, 2014, pp. 1-7. doi: 10.1109/APSIPA.2014.7041525In reference to IEEE copyrighted material which is used with permission in this thesis, the IEEE does not endorse any of Osaka University’s products or services. Internal or personal use of this material is permitted. If interested in reprinting/republishing IEEE copyrighted material for advertising or promotional purposes or for creating new collective works for resale or redistribution, please go to http://www.ieee.org/publications_standards/publications/rights/rights_link.html to learn how to obtain a License from RightsLink. If applicable, University Microfilms and/or ProQuest Library, or the Archives of Canada may supply single copies of the dissertation

Near-Minimal Gate Set Tomography Experiment Designs

Gate set tomography (GST) provides precise, self-consistent estimates of the noise channels for all of a quantum processor's logic gates. But GST experiments are large, involving many distinct quantum circuits. This has prevented their use on systems larger than two qubits. Here, we show how to streamline GST experiment designs by removing almost all redundancy, creating smaller and more scalable experiments without losing precision. We do this by analyzing the "germ" subroutines at the heart of GST circuits, identifying exactly what gate set parameters they are sensitive to, and leveraging this information to remove circuits that duplicate other circuits' sensitivities. We apply this technique to two-qubit GST experiments, generating streamlined experiment designs that contain only slightly more circuits than the theoretical minimum bounds, but still achieve Heisenberg-like scaling in precision (as demonstrated via simulation and a theoretical analysis using Fisher information). In practical use, the new experiment designs can match the precision of previous GST experiments with significantly fewer circuits. We discuss the prospects and feasibility of extending GST to three-qubit systems using our techniques.Comment: 11 pages, 6 figures, to be published in proceedings of 2023 IEEE International Conference on Quantum Computing and Engineering (QCE

Intelligent Circuits and Systems

ICICS-2020 is the third conference initiated by the School of Electronics and Electrical Engineering at Lovely Professional University that explored recent innovations of researchers working for the development of smart and green technologies in the fields of Energy, Electronics, Communications, Computers, and Control. ICICS provides innovators to identify new opportunities for the social and economic benefits of society.　 This conference bridges the gap between academics and R&D institutions, social visionaries, and experts from all strata of society to present their ongoing research activities and foster research relations between them. It provides opportunities for the exchange of new ideas, applications, and experiences in the field of smart technologies and finding global partners for future collaboration. The ICICS-2020 was conducted in two broad categories, Intelligent Circuits & Intelligent Systems and Emerging Technologies in Electrical Engineering

Fermilab SRF cryomodule operational experience

Fermi National Accelerator Laboratory is constructing an Advanced Accelerator Research and Development facility at New Muon Lab. The cryogenic infrastructure in support of the initial phase of the facility consists of two Tevatron style standalone refrigerators, cryogenic distribution system as well as an ambient temperature pumping system to achieve 2 K operations with supporting purification systems. During this phase of the project a single Type III plus 1.3 GHz cryomodule was installed, cooled and tested. Design constraints of the cryomodule required that the cryomodule individual circuits be cooled at predetermined rates. These constraints required special design solutions to achieve. This paper describes the initial cooldown and operational experience of a 1.3 GHz cryomodule using the New Muon Lab cryogenic system.Comment: 7 pp. Cryogenic Engineering Conference and International Cryogenic Materials Conference CEC-ICMC 2011 13-17 June 2011, Spokane, Washingto

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

15th IEEE International Conference on Electronics, Circuits and Systems, MaltaIn this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, PolóniaIn this paper a new structure for a multiplying-by-two amplifier is proposed. It is implemented by switching MOS capacitors with floating sources from inversion into depletion dropping the capacitance values in the amplification phase. Low-power is achieved since no operational amplifiers are required but, instead, simple sourcefollowers are used to provide the required isolation. Simulation results show that linearity levels better than 60dB and gain accuracies of better than 1.6% are achieved making this circuit well suited to be used in ultra low-power highspeed 6-to-8 bits pipeline or multi-stage algorithmic ADCs