7 research outputs found

    Artificial Intelligence in Hungary - The First 20 Years = Mesterséges intelligencia Magyarországon - az első 20 év

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    A magyarországi mesterséges intelligencia kutatások történetéről 1996-ban készített áttekintés 2006-ban korszerűsített változata, bőséges irodalom jegyzékkel

    Yapay sinir ağlarının uyarlanabilir donanımsal yapılarda gerçeklenmesi

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    06.03.2018 tarihli ve 30352 sayılı Resmi Gazetede yayımlanan “Yükseköğretim Kanunu İle Bazı Kanun Ve Kanun Hükmünde Kararnamelerde Değişiklik Yapılması Hakkında Kanun” ile 18.06.2018 tarihli “Lisansüstü Tezlerin Elektronik Ortamda Toplanması, Düzenlenmesi ve Erişime Açılmasına İlişkin Yönerge” gereğince tam metin erişime açılmıştır.Yapay Sinir Ağları (YSA'lar), biyolojik sinir sistemine dayalı elektronik modellerdir. YSA'lar girişlerden gelen verileri işleyen birbirine bağlı yapay nöronlardan oluşmaktadır. Bu mimariler, yazılım ya da donanım olarak gerçekleştirilebilirler. YSA'nın yazılım uygulamasının avantajı, tasarımcının YSA bileşenlerinin iç işleyişini bilmesine gerek olmamasıdır. Bununla birlikte, gerçek zamanlı uygulamalarda, yazılım tabanlı YSA'lar donanım tabanlı YSA'lardan daha yavaştır. YSA hesaplamaları paralel olarak gerçekleştirilmektedir ve paralel işlem için özel donanım aygıtları gereklidir. Birçok alandan araştırmacılar optimizasyon, sınıflandırma, kontrol, görüntü işleme vb. problemlerin çözümü için YSA donanım uygulamaları gerçekleştirmişlerdir. Bu uygulamalar, YSA'ların paralel doğasından yararlanmak için farklı türde cihazlar üzerinde gerçekleştirilmiştir. YSA'nın FPGA uygulamaları, yeniden yapılandırılabilir yapısı ve paralel mimarisi nedeniyle son yirmi yılda büyük ilgi uyandırmıştır. Bu tez çalışmasında, Quartus II şematik tasarım kullanılarak eğitilebilir çok katmanlı sinir ağı (MLNN) yapısının donanım uygulaması FPGA üzerinde tamamen kombinasyonel mantık olarak gerçekleştirilmiştir. Yapay sinir ağını eğitmek için eğim düşüm metodunu kullanan geri yayılım algoritması uygulanmıştır. Nümerik tanımlama için IEEE tek-hassasiyetli kayan-noktalı format kullanılmıştır. Bu çalışma aynı zamanda IEEE tek-hassasiyetli kayan-noktalı format ile tam uyumlu hızlı bir kayan noktalı toplayıcı, bir paralel çarpıcı ve bir sigmoid aktivasyon fonksiyonu bloğunu sunmaktadır. İşlemleri paralel olarak gerçekleştiren toplayıcı, paralel çarpıcı ve aktivasyon fonksiyonu bloğu tamamen kombinasyonel mantık olarak tasarlanmıştır. Bu yeni tasarımda, gecikmeyi azaltmak için kaydırma işlemlerinde kaydırmalı yazmaçlar yerine üç-durumlu tampon serileri kullanılmıştır. Üç-durumlu tampon serileri kullanıldığından kaydırma işlemi için saat darbesi gerekli değildir ve böylece sonuç tek bir çevrimde üretilir. Sadece kapı gecikmesi maliyetli önerilen tasarım, YSA'nın donanım uygulamaları için uygundur.Artificial Neural Networks (ANNs) are electronic models based on biological nervous system. ANNs are made up of interconnected artificial neurons which can process values from inputs. These architectures can be implemented either in software or in hardware. The advantage of the software implementation of ANN is that the designer does not need to know the inner workings of ANN components. However, in real time applications, software based ANNs are slower than hardware based ANNs. ANN computations are carried out in parallel and special hardware devices are required for parallel processing. Researchers from many disciplines have been performing ANN hardware implementations to solve a variety of problems in optimization, classification, control, image processing etc. These applications have been performed on different types of devices to take advantage of the parallel nature inherent to ANNs. FPGA implementations of ANN have aroused great interest during the last two decades due to its reconfigurable structure and parallel architecture. In this thesis, hardware implementation of trainable Multi Layer Neural Network (MLNN) structure on FPGA (Field Programmable Gate Array) is realized as entirely combinational logic by using Quartus II schematic design. The back propagation algortihm, which uses gradient descent metod is implemented in order to train the neural network. IEEE single-precision floating-point format is used for numerical description. This study also presents the hardware designs of a fast floating point adder, a parallel multiplier and a sigmoid activation function block that are fully compliant with the IEEE single-precision floating-point format. The adder, parallel multiplier and the activation function block are designed as entirely combinational logic that perform operations in parallel. In this novel design, tri state buffer series are used for shifting operations instead of shift registers for reducing latency. Because the use of tri-state buffer series, clock pulse is not required for shifting and thus the result is generated in only a single clock-cycle. The proposed design is suitable for hardware implementation of ANN at the cost of gate delays only

    Yapay sinir ağlarının uyarlanabilir donanımsal yapılarda gerçeklenmesi

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    06.03.2018 tarihli ve 30352 sayılı Resmi Gazetede yayımlanan “Yükseköğretim Kanunu İle Bazı Kanun Ve Kanun Hükmünde Kararnamelerde Değişiklik Yapılması Hakkında Kanun” ile 18.06.2018 tarihli “Lisansüstü Tezlerin Elektronik Ortamda Toplanması, Düzenlenmesi ve Erişime Açılmasına İlişkin Yönerge” gereğince tam metin erişime açılmıştır.Yapay Sinir Ağları (YSA'lar), biyolojik sinir sistemine dayalı elektronik modellerdir. YSA'lar girişlerden gelen verileri işleyen birbirine bağlı yapay nöronlardan oluşmaktadır. Bu mimariler, yazılım ya da donanım olarak gerçekleştirilebilirler. YSA'nın yazılım uygulamasının avantajı, tasarımcının YSA bileşenlerinin iç işleyişini bilmesine gerek olmamasıdır. Bununla birlikte, gerçek zamanlı uygulamalarda, yazılım tabanlı YSA'lar donanım tabanlı YSA'lardan daha yavaştır. YSA hesaplamaları paralel olarak gerçekleştirilmektedir ve paralel işlem için özel donanım aygıtları gereklidir. Birçok alandan araştırmacılar optimizasyon, sınıflandırma, kontrol, görüntü işleme vb. problemlerin çözümü için YSA donanım uygulamaları gerçekleştirmişlerdir. Bu uygulamalar, YSA'ların paralel doğasından yararlanmak için farklı türde cihazlar üzerinde gerçekleştirilmiştir. YSA'nın FPGA uygulamaları, yeniden yapılandırılabilir yapısı ve paralel mimarisi nedeniyle son yirmi yılda büyük ilgi uyandırmıştır. Bu tez çalışmasında, Quartus II şematik tasarım kullanılarak eğitilebilir çok katmanlı sinir ağı (MLNN) yapısının donanım uygulaması FPGA üzerinde tamamen kombinasyonel mantık olarak gerçekleştirilmiştir. Yapay sinir ağını eğitmek için eğim düşüm metodunu kullanan geri yayılım algoritması uygulanmıştır. Nümerik tanımlama için IEEE tek-hassasiyetli kayan-noktalı format kullanılmıştır. Bu çalışma aynı zamanda IEEE tek-hassasiyetli kayan-noktalı format ile tam uyumlu hızlı bir kayan noktalı toplayıcı, bir paralel çarpıcı ve bir sigmoid aktivasyon fonksiyonu bloğunu sunmaktadır. İşlemleri paralel olarak gerçekleştiren toplayıcı, paralel çarpıcı ve aktivasyon fonksiyonu bloğu tamamen kombinasyonel mantık olarak tasarlanmıştır. Bu yeni tasarımda, gecikmeyi azaltmak için kaydırma işlemlerinde kaydırmalı yazmaçlar yerine üç-durumlu tampon serileri kullanılmıştır. Üç-durumlu tampon serileri kullanıldığından kaydırma işlemi için saat darbesi gerekli değildir ve böylece sonuç tek bir çevrimde üretilir. Sadece kapı gecikmesi maliyetli önerilen tasarım, YSA'nın donanım uygulamaları için uygundur.Artificial Neural Networks (ANNs) are electronic models based on biological nervous system. ANNs are made up of interconnected artificial neurons which can process values from inputs. These architectures can be implemented either in software or in hardware. The advantage of the software implementation of ANN is that the designer does not need to know the inner workings of ANN components. However, in real time applications, software based ANNs are slower than hardware based ANNs. ANN computations are carried out in parallel and special hardware devices are required for parallel processing. Researchers from many disciplines have been performing ANN hardware implementations to solve a variety of problems in optimization, classification, control, image processing etc. These applications have been performed on different types of devices to take advantage of the parallel nature inherent to ANNs. FPGA implementations of ANN have aroused great interest during the last two decades due to its reconfigurable structure and parallel architecture. In this thesis, hardware implementation of trainable Multi Layer Neural Network (MLNN) structure on FPGA (Field Programmable Gate Array) is realized as entirely combinational logic by using Quartus II schematic design. The back propagation algortihm, which uses gradient descent metod is implemented in order to train the neural network. IEEE single-precision floating-point format is used for numerical description. This study also presents the hardware designs of a fast floating point adder, a parallel multiplier and a sigmoid activation function block that are fully compliant with the IEEE single-precision floating-point format. The adder, parallel multiplier and the activation function block are designed as entirely combinational logic that perform operations in parallel. In this novel design, tri state buffer series are used for shifting operations instead of shift registers for reducing latency. Because the use of tri-state buffer series, clock pulse is not required for shifting and thus the result is generated in only a single clock-cycle. The proposed design is suitable for hardware implementation of ANN at the cost of gate delays only

    Intelligent optical methods in image analysis for human detection

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    This thesis introduces the concept of a person recognition system for use on an integrated autonomous surveillance camera. Developed to enable generic surveillance tasks without the need for complex setup procedures nor operator assistance, this is achieved through the novel use of a simple dynamic noise reduction and object detection algorithm requiring no previous knowledge of the installation environment and without any need to train the system to its installation. The combination of this initial processing stage with a novel hybrid neural network structure composed of a SOM mapper and an MLP classifier using a combination of common and individual input data lines has enabled the development of a reliable detection process, capable of dealing with both noisy environments and partial occlusion of valid targets. With a final correct classification rate of 94% on a single image analysis, this provides a huge step forwards as compared to the reported 97% failure rate of standard camera surveillance systems.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

    A bilingual speech interface for New Zealand English to Māori

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    The 'Bilingual Speech Interface for New Zealand English to Māori ' is part of the 'Intelligent Human Computer Interfaces' project under 'Objective 3' of the 'Connectionist-Based Information Systems' programme (FoRST UOO606) Department of Information Science, University of Otago. The project experiments with artificial intelligent knowledge-based engineering methodologies and techniques for designing tools that utilise a hybrid system approach that is both adaptable and flexible to different speakers and languages-namely New Zealand English and Māori. Artificial neural networks, fuzzy rule-based inferencing techniques, genetic algorithms and multimedia based applications form the multiple paradigm approaches for solving real applied problems for speech generation. All are fundamental in the developmental direction of an intelligent human computer interface. Multimedia interfaces to databases use conventional software engineering techniques for the management, access and retrieval of information, therefore, implementing an interface application to access a speech and language database means that a change in computer interaction from manual to automatic control is facilitated between the user and the database. The 'Hybrid Neuro-Fuzzy Speech Recognition System' called HySpeech is based on isolated word recognition for New Zealand English that utilises an English-Māori lexical database to provide an automatic language translator or 'Talking Dictionary'. The current development with version two of HySpeech incorporates the advanced 'Fuzzy Neural Network' models with new 'Learning with Forgetting' algorithms for better speaker adaptive capabilities, an aggregation function provides cleaner phoneme compression and 'Self-Organising Maps' for phoneme and word lists-all to facilitate new language modelling techniques. The language information is housed in a separate database management system designed for HySpeech, it contains; the speakers' characteristics, English and Māori words, phonetic transcriptions and pronunciations, segmental labels, phoneme activation and co-ordinate vectors, and a growing set of digitised Māori speech examples. The interface component of HySpeech thus comprises and text examples from the aforementioned database, interactive dialogues, and a graphical user interface generated environment. Also, experiments in artificial language generation for speech synthesis provide the system with some knowledge and information about the languages. The system could therefore be capable of recreating a form of machine generated speech. Many approaches are available to facilitate synthesised speech, so by utilising the present methodologies and techniques, there is a future solution that can run parallel to the existing direction of HySpeech, for a complete bilingual speech interface. Given that there is presently no operational system that can synthesise New Zealand English and Māori speech, this thesis will also provide some basis to facilitate the further research and development in that area.ndrewes, M. and Tamblyn, R. (1994) On Call™ Innovative Language Learning Systems, Language Learning Centre, University of Otago, Dunedin. Apple Computer Inc. (1991) Inside Macintosh, Volume VI. Addison Wesley. Apple Computer Inc. (1996) Inside Macintosh, On-Line Version. [http://speech.apple.com/dev/insidemac/] Apple Computer Inc. (1997) PlainTalk: An Apple Speech Technology White Paper. [http://speech.apple.com/] Bäckström, C. and Sandewall, E. (1994) Current Trends in AI Planning. EWSP’93 – 2nd European Workshop on Planning, IOS Press, Amsterdam. Barlow, C. (1990a) An Alternative Format for Maori Archival Materials, Archifacts, April 1990, pp. 22-28. Barlow, C. (1990b) Me Ako Taatou i Te Reo Maaori , By Bruce Biggs, Uniprint, Orakei. Barlow, C. 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In Proceedings NAMMSAT Conference, October 1997, Massey University, Palmerston North. Kilgour, R. “Hybrid Fuzzy Systems and Neural Networks for Speech Recognition.” Unpublished M.Sc. (Cognitive) thesis, University of Otago, 1996. Kilgour, R. (1997) Report on file formats for sound and speech files. Department of Information Science, University of Otago. Knowles, M. (1983) Andragogy: An Emerging Technology for Adult Learning, M. Tight (ed.) In, Adult Learning and Education. London: Open University. 53-70. Kohonen, T. (1990) The Self-Organizing Map, Proceedings of the IEEE, vol.78, N-9, pp. 1464-1479. Kohonen, T. (1997) Self-Organizing Maps, Second Edition, Springer-Verlag, New York. Kosko, B. (1992) Neural Networks and Fuzzy Systems: A Dynamical Approach to Machine Intelligence, Prentice Hall, New Jersey. Kozma, R., Sakuma, M., Yokoyama, Y., Kitamura, M. (1996) On the accuracy of mapping by neural networks trained with backpropagation with forgetting, Neurocomputing, 13, pp. 295- 311. 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