Thermal rectification in asymmetric U-shaped graphene flakes

In this paper, we study the thermal rectification in asymmetric U-shaped graphene flakes by using nonequilibrium molecular dynamics simulations. The graphene flakes are composed by a beam and two arms. It is found that the heat flux runs preferentially from the wide arm to the narrow arm which indicates a strong rectification effect. The dependence of the rectification ratio upon the heat flux, the length and the width of the beam, the length and width of the two arms are studied. The result suggests a possible route to manage heat dissipation in U-shaped graphene based nanoelectronic devices.Comment: 3 pages, 4 figure

Capacity, Fidelity, and Noise Tolerance of Associative Spatial-Temporal Memories Based on Memristive Neuromorphic Network

We have calculated the key characteristics of associative (content-addressable) spatial-temporal memories based on neuromorphic networks with restricted connectivity - "CrossNets". Such networks may be naturally implemented in nanoelectronic hardware using hybrid CMOS/memristor circuits, which may feature extremely high energy efficiency, approaching that of biological cortical circuits, at much higher operation speed. Our numerical simulations, in some cases confirmed by analytical calculations, have shown that the characteristics depend substantially on the method of information recording into the memory. Of the four methods we have explored, two look especially promising - one based on the quadratic programming, and the other one being a specific discrete version of the gradient descent. The latter method provides a slightly lower memory capacity (at the same fidelity) then the former one, but it allows local recording, which may be more readily implemented in nanoelectronic hardware. Most importantly, at the synchronous retrieval, both methods provide a capacity higher than that of the well-known Ternary Content-Addressable Memories with the same number of nonvolatile memory cells (e.g., memristors), though the input noise immunity of the CrossNet memories is somewhat lower

Nanoelectronic thermometers optimised for sub-10 millikelvin operation

We report the cooling of electrons in nanoelectronic Coulomb blockade thermometers below 4 mK. Above 7 mK the devices are in good thermal contact with the environment, well isolated from electrical noise, and not susceptible to self-heating. This is attributed to an optimised design that incorporates cooling fins with a high electron-phonon coupling and on-chip electronic filters, combined with a low-noise electronic measurement setup. Below 7 mK the electron temperature is seen to diverge from the ambient temperature. By immersing a Coulomb Blockade Thermometer in the 3He/4He refrigerant of a dilution refrigerator, we measure a lowest electron temperature of 3.7 mK.Comment: 11 pages, 4 figures. (Fixed fitted saturation T_e on p9

Mathematical Estimation of Logical Masking Capability of Majority/Minority Gates Used in Nanoelectronic Circuits

In nanoelectronic circuit synthesis, the majority gate and the inverter form the basic combinational logic primitives. This paper deduces the mathematical formulae to estimate the logical masking capability of majority gates, which are used extensively in nanoelectronic digital circuit synthesis. The mathematical formulae derived to evaluate the logical masking capability of majority gates holds well for minority gates, and a comparison with the logical masking capability of conventional gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR is provided. It is inferred from this research work that the logical masking capability of majority/minority gates is similar to that of XOR/XNOR gates, and with an increase of fan-in the logical masking capability of majority/minority gates also increases