On the Capacity of Multilevel NAND Flash Memory Channels

In this paper, we initiate a first information-theoretic study on multilevel NAND flash memory channels with intercell interference. More specifically, for a multilevel NAND flash memory channel under mild assumptions, we first prove that such a channel is indecomposable and it features asymptotic equipartition property; we then further prove that stationary processes achieve its information capacity, and consequently, as its order tends to infinity, its Markov capacity converges to its information capacity; eventually, we establish that its operational capacity is equal to its information capacity. Our results suggest that it is highly plausible to apply the ideas and techniques in the computation of the capacity of finite-state channels, which are relatively better explored, to that of the capacity of multilevel NAND flash memory channels.Comment: Submitted to IEEE Transactions on Information Theor

The efficient recovery of deleted data from NAND flash memory

NAND flash memory is used in flash drives, smart phones, and memory cards for digital cameras. While there are ways to recover data from deleted memory, there are no universal or efficient ways to recover data from NAND flash memory. When a user clicks “delete” on a file in this type of memory, the file is not necessarily deleted, but may just be hidden. This means these files are still on the chip, but are inaccessible through normal means. The ability to recover this lost data could help computer forensic examiners during investigations and corporations working to use secure deletion techniques of confidential files. This project will provide a potential solution to recovering data from NAND flash memory. This research is a continuation of previous research where some code was written in Python using processes. The previous attempt to write this software resulted in software that was slow and would not scale well to large storage devices. This research explores whether software can be rewritten to take advantage of parallel computer execution on multiple processor cores to run and finish execution in a reasonable amount of time that would scale well to larger chip sizes, creating an efficient means of analyzing deleted data from NAND flash memory

NAND Flash Memory Characterization

The NAND technology has become a popular research area and implementation choice due to its non-volatile flash memory characteristics. There are many engineering challenges when it comes to NAND technology. Some of the limiting factors are reducing the transistor width and increasing read and write performance. The device physics for NAND floating gate cell technology also introduces challenges. Using a floating gate transistor that can address up to 4 bits per cell allows for higher density. However, this introduces a higher internal current leakage that can cause read and program inaccuracies. With floating-gate 3D NAND technology, we are able to better the data retention and have better QLC (Quad-Level Cell) capability. 3D NAND technology has a series of memory cells interconnected that can achieve higher data density and increased storage capacity. In this research, the Gen-4 NAND Flash device functionality is explored by design validation to achieve higher solid-state drive performance. This technology is 144-Layer QLC NAND Flash which is 1024Gb in density. My contributions are implemented showing improved read and write performance for customer operations and how inaccuracies are dealt with from a software and hardware perspective. Silicon wafer testing is also explored to fully characterize and analyze the problem

NAND型フラッシュメモリセルの研究

This paper presents the device technologies of NAND Flash memory to realize low bit cost and high reliability. First, planar (two-dimensional) NAND Flash memory cells are discussed. Four types of NAND Flash memory cells of the LOCOS (LOCal Oxidation of Silicon) isolation cell, the SA-STI cell (Self-Aligned Shallow Trench Isolation cell) with FG wing, the SA-STI cell without FG wing, and SWATT cell (Side WAll Transfer Transistor cell) have been proposed and developed. By using these proposed memory cell, NAND Flash memory cell has been scaled down over 20 years to achieve small memory die size, high performance, and high reliability.……広島大学(Hiroshima University)博士(工学)Engineeringdoctora

Methods for Threshold Voltage Setting of String Select Transistors in Channel Stacked NAND Flash Memory

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 박병국.Since recent mobile electronic devices such as tablets, laptops, smartphones, or solid-state drives (SSDs) have started to adopt the NAND flash memory as their main data storage device, the demand for low-cost and high-density NAND flash memories has experienced a rapid increase. However, some problems such as the limitations of photolithography technology, cell-to-cell interference, and reduction of the number of electrons stored in floating gates have hindered the downscaling of floating-gate NAND flash memories. To overcome the NAND scaling issues, several types of three-dimensional (3D) stacked charge-trap NAND flash memories, which have been developed based on the bit-cost scalable (BiCS) technology introduced by Toshiba, have been widely investigated, owing to their scalability, ease of fabrication, and coupling-free characteristics. 3D-stacked NAND flash memory architectures can be divided into two categories. The first is the gate-stacked NAND flash memory, in which current flows through a vertical channel while the gates are shared horizontally by all the strings. The second category consists of channel-stacked NAND flash memories, in which the current flows through the horizontally stacked channel and the gates are shared vertically by all the strings. In 3D-stacked NAND flash memory architectures. The channel-stacked type presents several outstanding advantages in terms of minimal unit cell size, bit line (BL) pitch scaling, use of a single-crystalline Si channel by Si/SiGe epitaxial growth process, and degradation characteristics of read currents caused by the increase in the number of stacked layers. However, compared with the gate-stacked type, the channel-stacked type presents critical issues that hinder its use in commercial applications, such as complex array architectures and decoding of the stacked layers. To overcome these problems, our group has recently reported channel-stacked arrays with layer selection by multilevel (LSM) operation. However, the array architecture and operation scheme setting the string select transistors (SSTs) with multilevel states should be simplified further to enable commercialization. In this dissertation, a simplified channel-stacked array with LSM operation is proposed. In addition, new SST threshold voltage (Vth) setting methods to set all the SSTs on each layer to the targeted Vths values are introduced and verified by using technology computer-aided design (TCAD) simulations and measurements in fabricated pseudo-SLSM. Furthermore, various disturbance phenomena that could occur during basic memory operations such as erase, program, and read are analyzed, and schemes for mitigating these disturbances are proposed and verified.Chapter1 Three-Dimensional Stacked NAND Flash Memory 1 1.1 Introduction to Three-Dimensional Stacked NAND Flash Memory 1 1.2 Gate Stack Type NAND Flash Memory 8 1.3 Channel Stack Type NAND Flash Memory 17 1.4 Comparison between Gate Stack Type NAND Flash and Channel Stack Type NAND Flash 24 Chapter2 Channel Stacked NAND Flash Memory with Layer Selection by Multilevel Operation 28 2.1 LSM and Channel Stacked NAND Flash Architecture Design 28 2.2 Operation Scheme of Channel Stacked NAND Flash Memory with LSM 36 2.2.1 Stacked SST Initialization to Enable LSM 36 2.2.2 Read Operation with LSM 38 2.2.3 Program/Erase Operation with LSM 42 2.3 Comparison with Conventional Channel Stacked NAND Flash Memory Architecture 47 Chapter3 Methods for Setting String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory 50 3.1 Method for Setting SST Vth Using One Erase Operation 50 3.2 Method for Setting SST Vth Using Dummy SSTs 60 Chapter4 Reliability Issues During LSM in Channel Stacked NAND Flash Memory 69 4.1 Program Disturbance in SLSM 69 4.2 Read Disturbance in SLSM 84 Chapter5 Application to General NAND Flash Memory 95 Chapter6 Conclusions 103 Bibliography 106 Abstract in Korean 119Docto