DESEMPEÑO DE UN CORRELADOR HIBRIDO DE TRANSFORMACION CONJUNTA A UNA RAPIDEZ DE PROCESAMIENTO MAYOR A LA VELOCIDAD DE VIDEO,CON UN SOLO PROCESADOR DIGITAL

En este trabajo un correlador híbrido de transformación conjunta JTC de bajo costo que usa de manera complementaria las propiedades ópticas y las electrónicas, es implementado experimentalmente. Este correlador resuelve los mayores inconvenientes de un JTC óptico convencional. El JTC híbrido usa un único procesador digital de señales DSP para procesar la densidad espectral de energía conjunta JPS que es obtenida por vía óptica. La JPS de la escena y la referencia, colocadas en un modulador espacial de luz que actúa como plano de entrada, es obtenida en el plano focal imagen del procesador óptico. La adquisición digital de la JPS se hace mediante un sensor CCD que actúa como entrada al DSP. La reducción del pico central de energía de la JPS se realiza mediante un filtro óptico apodizante justo antes del sensor. Finalmente, el DSP realiza una transformación de Fourier digital de la JPS, controla todo el proceso y calcula las métricas de desempeño del correlador. Los requerimientos computacionales se reducen significativamente con la simetría hermítica de la transformada de Fourier realizada mediante el DSP para imágenes reales, esto es, que su velocidad de procesamiento lo hace hábil también para detectar objetos en escenas móviles

Implementation and Applications of Logarithmic Signal Processing on an FPGA

This thesis presents two novel algorithms for converting a normalised binary floating point number into a binary logarithmic number with the single-precision of a floating point number. The thesis highlights the importance of logarithmic number systems in real-time DSP applications. A real-time cross-correlation application where logarithmic signal processing is used to simplify the complex computation is presented. The first algorithm presented in this thesis comprises two stages. A piecewise linear approximation to the original logarithmic curve is performed in the first stage and a scaled-down normalised error curve is stored in the second stage. The algorithm requires less than 20 kbits of ROM and a maximum of three small multipliers. The architecture is implemented on Xilinx's Spartan3 and Spartan6 FPGA family. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6. Both solutions have a pipeline latency of two clocks. The operating speed increases to 71.4 MHz and 160 MHz respectively when the pipeline latencies increase to eight clocks. The proposed algorithm is further improved by using a PWL (Piece-Wise Linear) approximation of the transform curve combined with a PWL approximation of a scaled version of the normalized segment error. A hardware approach for reducing the memory with additional XOR gates in the second stage is also presented. The architecture presented uses just one 18k bit Block RAM (BRAM) and synthesis results indicate operating frequencies of 93 and 110 MHz when implemented on the Xilinx Spartan3 and Spartan6 devices respectively. Finally a novel prototype of an FPGA-based four channel correlation velocimetry system is presented. The system operates at a higher sampling frquency than previous published work and outputs the new result after every new sample it receives. The system works at a sampling frequency of 195.31 kHz and a sample resolution of 12 bits. The prototype system calculates a delay in a range of 0 to 2.6 ms with a resolution of 5.12 us