Multiprocessor raster plotting

A scalable multiprocessor raster image processor that generates printed circuit plots in alternating band buffers is described. Synchronous raster plotting systems and the development of mask creation for producing printed circuits are reviewed. The general architecture of the multiprocessing system that rasterizes printed circuit plot descriptions, and its graphics, load prediction, and facet size computation operations are discussed. Performance analysis results of two versions of the multiprocessor architecture, one with four rasterization transputers and the other with eight, are presente

Functional requirements document for the Earth Observing System Data and Information System (EOSDIS) Scientific Computing Facilities (SCF) of the NASA/MSFC Earth Science and Applications Division, 1992

Five scientists at MSFC/ESAD have EOS SCF investigator status. Each SCF has unique tasks which require the establishment of a computing facility dedicated to accomplishing those tasks. A SCF Working Group was established at ESAD with the charter of defining the computing requirements of the individual SCFs and recommending options for meeting these requirements. The primary goal of the working group was to determine which computing needs can be satisfied using either shared resources or separate but compatible resources, and which needs require unique individual resources. The requirements investigated included CPU-intensive vector and scalar processing, visualization, data storage, connectivity, and I/O peripherals. A review of computer industry directions and a market survey of computing hardware provided information regarding important industry standards and candidate computing platforms. It was determined that the total SCF computing requirements might be most effectively met using a hierarchy consisting of shared and individual resources. This hierarchy is composed of five major system types: (1) a supercomputer class vector processor; (2) a high-end scalar multiprocessor workstation; (3) a file server; (4) a few medium- to high-end visualization workstations; and (5) several low- to medium-range personal graphics workstations. Specific recommendations for meeting the needs of each of these types are presented

Remote access for NAS: Supercomputing in a university environment

The experiment was designed to assist the Numerical Aerodynamic Simulation (NAS) Project Office in the testing and evaluation of long haul communications for remote users. The objectives of this work were to: (1) use foreign workstations to remotely access the NAS system; (2) provide NAS with a link to a large university-based computing facility which can serve as a model for a regional node of the Long-Haul Communications Subsystem (LHCS); and (3) provide a tail circuit to the University of Colorado a Boulder thereby simulating the complete communications path from NAS through a regional node to an end-user

Graphical representation of data for a multiprocessor platform emulating spiking neural networks

Research in the eld of simulating large-scale spiking neural networks (SNN) has been carried out within the frame of Perplexus a European-funded re- search project based on a university consortium. In this project, a semi- custom electronic device called Ubichip has been designed. The mode of interest of this chip to emulate SNNs is based on a SIMD (Single-Instruction Multiple-Data) multiprocessor machine. The software for generating the as- sembly containing simulation of Iglesias-Villa spiking neural network model was also developed within that project and it is currently being successfully used for running neural network emulation on Ubichip. The tools developed so far are useful for debugging by simulation, but in order to evaluate the behavior of SNN being emulated, two needs arose: real- time monitoring of the network evolution and a higher-level, understandable visualization solution. First, the existing software that was developed in the Perplexus project has been analyzed. After examining all available solutions, including writing a standalone dedicated program, it was nally decided to develop the so-called Ubiplot plug-in. The reason was to take advantage of the existing Ubimanager environment. The development started by verifying the communication with the Ubichip, so simple waveforms for data in a given address in the Ubichip's RAM were implemented. Then the plug-in was extended with histogram and raster plots that are accessing multiple locations of the memory in each execution step. This led to the creation of the variable map that de nes the program's variables and their precise placement in the RAM. At the end simple logging facility and possibility to save and restore the layout of the plots were added. This thesis describes the Ubiplot and the development e ort put in its creation

A Multiprocessor three-dimensional graphics systems.

by Hui Chau Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1991.Includes bibliographical references.ABSTRACT --- p.iACKNOWLEDGEMENTS --- p.iiTABLE OF CONTENTS --- p.iiiChapter CHAPTER 1 --- INTRODUCTIONChapter 1.1 --- Computer Graphics Today --- p.2Chapter 1.1.1 --- 3D Graphics Synthesis Techniques --- p.2Chapter 1.1.2 --- Hardware-assisted Computer Graphics --- p.4Chapter 1.2 --- About The Thesis --- p.5Chapter CHAPTER 2 --- GRAPHICS SYSTEM ARCHITECTURESChapter 2.1 --- Basic Structure of a Graphics Subsystem --- p.8Chapter 2.2 --- VLSI Graphics Chips --- p.9Chapter 2.2.1 --- The CRT Controllers --- p.10Chapter 2.2.2 --- The VLSI Graphics Processors --- p.11Chapter 2.2.3 --- Design Philosophies for VLSI Graphics Processors --- p.12Chapter 2.3 --- Graphics Boards --- p.14Chapter 2.3.1 --- The ARTIST 10 Graphics Controller --- p.14Chapter 2.3.2 --- The MATROX PG-1281 Graphics Controller --- p.16Chapter 2.4 --- High-end Graphics System Architectures --- p.17Chapter 2.4.1 --- Graphics Accelerator with Multiple Functional Units --- p.18Chapter 2.4.2 --- Parallel Processing Graphics Systems --- p.18Chapter 2.4.3 --- The Parallel Processor Architecture --- p.19Chapter 2.4.4 --- The Pipelined Architecture --- p.21Chapter 2.5 --- Comparisons and Discussions --- p.22Chapter 2.5.1 --- Parallel Processors versus Pipelined Processing --- p.23Chapter 2.5.2 --- Parallel Processors versus Multiple Functional Units --- p.23Chapter 2.6 --- Summary of High-end Graphics Systems --- p.24Chapter CHAPTER 3 --- AN ISA 3D GRAPHICS DISPLAY SERVERChapter 3.1 --- Common ISA Graphics Cards --- p.26Chapter 3.1.1 --- Standard Video Display Cards --- p.26Chapter 3.1.2 --- Graphics Processing Boards --- p.27Chapter 3.2 --- A Depth Processor for the ISA computers --- p.28Chapter 3.2.1 --- The Z-buffer Algorithm for HLHSR --- p.28Chapter 3.2.2 --- Our Hardware Solution for HLHSR --- p.29Chapter 3.2.3 --- Design of the Depth Processor --- p.31Chapter 3.2.4 --- Structure of the Depth Processor --- p.34Chapter 3.2.5 --- The Depth Processor Operations --- p.35Chapter 3.2.6 --- Software Support --- p.40Chapter 3.2.7 --- Performance of the Depth Processor --- p.44Chapter 3.3 --- A VGA Accelerator for the ISA Computers --- p.45Chapter 3.3.1 --- Display Buffer Structure of the SuperVGA --- p.46Chapter 3.3.2 --- Design of the VGA Accelerator --- p.47Chapter 3.3.3 --- Structure of the VGA Accelerator --- p.49Chapter 3.3.4 --- Combining the VGA Accelerator and the Depth Processor --- p.51Chapter 3.3.5 --- Actual Performance of the DP-VA Board --- p.54Chapter 3.3.6 --- 3D Graphics Applications Using the DP-VA Board --- p.55Chapter 3.4 --- A 3D Graphics Display Server --- p.57Chapter 3.5 --- Host Connection for the 3D Graphics Display Server --- p.59Chapter 3.5.1 --- The Single Board Computers --- p.60Chapter 3.5.2 --- The VME-to-ISA bus convenor --- p.61Chapter 3.5.3 --- Structure of the VME-to-ISA Bus Convertor --- p.61Chapter 3.5.4 --- Communications through the bus convertor --- p.64Chapter 3.6 --- Physical Construction of the DP-VA Board and the Bus Convertor --- p.65Chapter 3.7 --- Summary --- p.66Chapter CHAPTER 4 --- A MULTI-i860 3D GRAPHICS SYSTEMChapter 4.1 --- The i860 Processor --- p.69Chapter 4.2 --- Design of a Multiprocessor 3D Graphics System --- p.70Chapter 4.2.1 --- A Reconfigurable Processor-Pipeline System --- p.72Chapter 4.2.2 --- The Depth-Processing Unit --- p.73Chapter 4.2.3 --- A Multiprocessor Graphics System --- p.75Chapter 4.3 --- Structure of the Multi-i860 3D --- p.77Chapter 4.3.1 --- The 64-bit-wide Global Data Buses --- p.77Chapter 4.3.2 --- The 1280x1024 True-colour Display Unit --- p.79Chapter 4.3.3 --- The Depth Processing Unit --- p.82Chapter 4.3.4 --- The i860 Processing Units --- p.84Chapter 4.3.5 --- The System Control Unit --- p.87Chapter 4.3.6 --- Performance Prediction --- p.89Chapter 4.4 --- Summary --- p.90Chapter CHAPTER 5 --- CONCLUSIONSChapter 5.1 --- The 3D Graphics Synthesis Pipeline ……… --- p.91Chapter 5.2 --- 3D Graphics Hardware --- p.91Chapter 5.3 --- Design Approach for the ISA 3D Graphics Display Server --- p.92Chapter 5.4 --- Flexibility in the Multi-i860 3D Graphics System --- p.93Chapter 5.5 --- Future Work --- p.94Chapter APPENDIX A --- DISPLAYING REALISTIC 3D SCENESChapter A.1 --- Modelling 3D Objects in Boundary Representation --- p.96Chapter A.2 --- Transformations of 3D scenes --- p.98Chapter A.2.1 --- Composite Modelling Transformation --- p.98Chapter A.2.2 --- Viewing Transformations --- p.99Chapter A.2.3 --- Projection --- p.102Chapter A.2.4 --- Window to Viewport Mapping --- p.104Chapter A.3 --- Implementation of the Viewing Pipeline --- p.105Chapter A.3.1 --- Defining the View Volume --- p.105Chapter A.3.2 --- Normalization of The View Volume --- p.106Chapter A.3.3 --- The Overall Transformation Pipeline --- p.108Chapter A.4 --- Rendering Realistic 3D Scenes --- p.108Chapter A.4.1 --- Scan-conversion of Lines and Polygons --- p.108Chapter A.4.2 --- Hidden Surface Removal --- p.109Chapter A.4.3 --- Shading --- p.112Chapter A.4.4 --- The Complete 3D Graphics Pipeline --- p.114Chapter APPENDIX B --- DEPTH PROCESSOR DESIGN DETAILSChapter B.l --- PAL Definitions --- p.116Chapter B.2 --- Circuit Diagrams --- p.118Chapter B.3 --- Depth Processor User's Guide --- p.121Chapter APPENDIX C --- VGA ACCELERATOR DESIGN DETAILSChapter C.1 --- PAL Definitions --- p.124Chapter C.2 --- Circuit Diagram --- p.125Chapter C.3 --- The DP-VA User's Guide --- p.127Chapter APPENDIX D --- VME-TO-ISA BUS CONVERTOR DESIGN DETAILSChapter D.1 --- PAL Definitions --- p.131Chapter D.2 --- Circuit Diagrams --- p.133Chapter APPENDIX E --- 3D GRAPHICS LIBRARY ROUTINES FOR THE DP-VA BOARDChapter E.1 --- 3D Drawing Routines --- p.136Chapter E.2 --- 3D Transformation Routines --- p.137Chapter E.3 --- Shading Routines --- p.138Chapter APPENDIX F --- PIPELINE CONFIGURATIONS FOR N PROCESSORSREFERENCE

Graphical representation of data for a multiprocessor platform emulating spiking neural networks

Research in the eld of simulating large-scale spiking neural networks (SNN) has been carried out within the frame of Perplexus a European-funded re- search project based on a university consortium. In this project, a semi- custom electronic device called Ubichip has been designed. The mode of interest of this chip to emulate SNNs is based on a SIMD (Single-Instruction Multiple-Data) multiprocessor machine. The software for generating the as- sembly containing simulation of Iglesias-Villa spiking neural network model was also developed within that project and it is currently being successfully used for running neural network emulation on Ubichip. The tools developed so far are useful for debugging by simulation, but in order to evaluate the behavior of SNN being emulated, two needs arose: real- time monitoring of the network evolution and a higher-level, understandable visualization solution. First, the existing software that was developed in the Perplexus project has been analyzed. After examining all available solutions, including writing a standalone dedicated program, it was nally decided to develop the so-called Ubiplot plug-in. The reason was to take advantage of the existing Ubimanager environment. The development started by verifying the communication with the Ubichip, so simple waveforms for data in a given address in the Ubichip's RAM were implemented. Then the plug-in was extended with histogram and raster plots that are accessing multiple locations of the memory in each execution step. This led to the creation of the variable map that de nes the program's variables and their precise placement in the RAM. At the end simple logging facility and possibility to save and restore the layout of the plots were added. This thesis describes the Ubiplot and the development e ort put in its creation

Workstation graphics capabilities for the 1990's and beyond

We present in this paper a look at the future graphics capabilities of the workstation. We begin by examining the cycles of special hardware development that have occurred for graphics systems in general. We show how the current evolution of the graphics workstation is a direct response to applications user desires for higher performance, graphics systems. The software and hardware levels that perform the input and output graphics operations for the workstation are described with an eye towards categorizing future graphics capabilities. The implementation of those levels in the Silicon Graphics, Inc. IRIS is cited as an example of the leading edge for graphics workstation is presented as a continuation of the historical response to applications user desires for ever higher performance, interactive systems. Categories and Subject Descriptors: I.3.1 (Hardware Architecture): architectures, parallel processing. VLSI implementations; I.3.2 (Graphics Systems): multiprocessing systems; I.3.3 (Picture/Image Generation): surface visualization: I.3.6 (Methodology and Techniques): contouring, interactive systems, parallel processing; I.3.7 (Three-Dimensional Graphics and Realism): line drawings, line generation algorithms, real-tlime graphics, surface plotting, surface visualization, surface; I.3.m (Miscellaneous): VSLI; Additional keywords and phrases: contour sufrace display generation; Real-time display generation; Graphics workstationssupported by in part by the Foundation Research Program of the Naval Postgraduate Schoolhttp://archive.org/details/workstationgraph00zydafunds provided by the Chief of Naval Researc

Conceptual design study for an advanced cab and visual system, volume 2

The performance, design, construction and testing requirements are defined for developing an advanced cab and visual system. The rotorcraft system integration simulator is composed of the advanced cab and visual system and the rotorcraft system motion generator, and is part of an existing simulation facility. User's applications for the simulator include rotorcraft design development, product improvement, threat assessment, and accident investigation