Fast and power efficient 16×16 Array of Array multiplier using Vedic Multiplication

This paper discusses about "Array of Array" multiplier which is a derivative of Braun Array Multiplier. Braun array are much suitable for VLSI implementation because of its less space complexity though it shows larger time complexity, on the other hand tree multipliers have time complexity of O(log n) but are less suitable for VLSI implementation since, being less regular; they require larger total routing length, which leads to performance degradation; simply put, they show higher space complexity. The main advantage of "Array of Array" multipliers is its inherent ability to reduce both time and space complexity [7] [8] with intermediate relative performance [7]. In this paper a 16×16 unsigned 'Array of Array' multiplier circuit is designed with hierarchical structuring, it has been optimized using Vedic Multiplication Sutra (Algorithm) "Urdhva Triyagbhyam" [1][6] and Karatsuba-Ofman algorithm[2]. The proposed algorithm is useful for math coprocessors in the field of computers. Algorithm is implemented on SPARTAN-3E FPGA (Field Programmable Gate Array). The proposed multiplier implementation shows large reduction in average power dissipation and in time delay as compared to Booth encoded radix-4 multiplier

Comparison Among Booth’s and Pekmestzi’s Algorithms for the Multiplication of Two Numbers

A comparison between two different methods of multiplication of two 8-bit numbers is presented. This methods are the Booth’s algorithm and the algorithm proposed by Kiamal Z. Pekmestzi [1]. The general objective is to show the benefits and the advantages obtained if it’s used one of this algorithms over the other. This multipliers have low circuit complexity permitting high-speed operations and the interconnections of the cells are regular. This is the reason why the results shown was obtained using VHDL realization on a FPGA XC4010XL by Xilinx.Consejo de Ciencia y Tecnología del Estado de GuanajuatoConsejo Nacional de Ciencia y TecnologíaUniversidad de GuanajuatoXili

Optimization of Speed using Compressors

The main objective of this Review is to provide high speed solutions for Very Large Scale Integration (VLSI) designers. Especially, we want focuses on the reduction of the time delay, which is showing an ever-increasing growth with the scaling down of the technologies. Various techniques at the different levels of the design process have been implemented to reduce the time delay at the circuit, architectural and system level. The high performance is obtained by using a new hierarchical structure, These adders are called compressors. These compressors make the multipliers faster as compared to the conventional design .

Design and realization of a high speed 64 x 64 - bit multiplier for low power applications

Wireless communication systems, including third generation cellular radio systems and wireless LANs, have become tremendously popular in recent years. These systems can be implemented using various platforms, like digital signal processors, ASICs and FPGAs. Most digital signal processing systems incorporate a multiplication unit to implement algorithms such as correlations, convolution, filtering and frequency analysis. These algorithms are used in applications such as finite impulse filters (FIR), infinite impulse filters (IIR), discrete cosine transforms (DCT) and fast Fourier transforms (FFT). Moreover, there has been a rapid increase in the popularity of portable and wireless electronic devices, like laptop computers, portable video players and cellular phones, which rely on embedded digital signal processors. Since the desire is to design digital systems for communication applications at best performance without power sacrifices, the need for high performance and low power multipliers is inevitable. Since multiplication is one of the most critical operations in many computational systems, there have been many algorithm proposals in the literature to perform multiplication, each offering different advantages and having tradeoffs in terms of speed, circuit complexity, area and power consumption. This thesis focuses on an ASIC implementation of a multiplexer-based multiplication method, an efficient algorithm which is applicable to low power applications. Recently, it has been proved that the multiplexer-based multiplier outperforms the modified Booth multiplier both in speed and power dissipation by 13% to 26%, due to small internal capacitance. After analyzing the performance characteristics of conventional multiplier types, it is observed that the one designed using multiplexer-based multiplication algorithm is more advantageous, especially when the size of the multiplied numbers is small. In order to verify the superiorities of this algorithm, we performed an implementation, in which the bit size of the multiplicand and the multiplier is comparably large. Thus, realization of a 64 x 64-bit multiplier block has been done in 0.35 M [micron] CMOS technology using Cadence Design Framework tools. The final multiplier structure operates at 12.8 ns with an approximate dynamic power consumption of 1mW. Also, using the same algorithm, another block of 32-bit x 32-bit multiplier is designed and is sent for fabrication

Ressourceneffiziente Realisierung pulscodierter neuronaler Netze

Tim KaulmannPaderborn, Univ., Diss., 200