DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

A Hierachical Infrastrucutre for SOC Test Management

HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system

A programmable BIST architecture for clusters of Multiple-Port SRAMs

This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timin

Characteristics and capacities of the NASA Lewis Research Center high precision 6.7- by 6.7-m planar near-field scanner

A very precise 6.7- by 6.7-m planar near-field scanner has recently become operational at the NASA Lewis Research Center. The scanner acquires amplitude and phase data at discrete points over a vertical rectangular grid. During the design phase for this scanner, special emphasis was given to the dimensional stability of the structures and the ease of adjustment of the rails that determine the accuracy of the scan plane. A laser measurement system is used for rail alignment and probe positioning. This has resulted in very repeatable horizontal and vertical motion of the probe cart and hence precise positioning in the plane described by the probe tip. The resulting accuracy will support near-field measurements at 60 GHz without corrections. Subsystem design including laser, electronic and mechanical and their performance is described. Summary data are presented on the scan plane flatness and environmental temperature stability. Representative near-field data and calculated far-field test results are presented. Prospective scanner improvements to increase test capability are also discussed

On-Orbit Validation of a Framework for Spacecraft-Initiated Communication Service Requests with NASA's SCaN Testbed

We design, analyze, and experimentally validate a framework for demand-based allocation of high-performance space communication service in which the user spacecraft itself initiates a request for service. Leveraging machine-to-machine communications, the automated process has potential to improve the responsiveness and efficiency of space network operations. We propose an augmented ground station architecture in which a hemispherical-pattern antenna allows for reception of service requests sent from any user spacecraft within view. A suite of ground-based automation software acts upon these direct-to-Earth requests and allocates access to high-performance service through a ground station or relay satellite in response to immediate user demand. A software-defined radio transceiver, optimized for reception of weak signals from the helical antenna, is presented. Design and testing of signal processing equipment and a software framework to handle service requests is discussed. Preliminary results from on-orbit demonstrations with a testbed onboard the International Space Station are presented to verify feasibility of the concept

On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation