Full-Duplex Massive MIMO Relaying Systems with Low-Resolution ADCs

International audienceThis paper considers a multipair amplify-and-forward massive MIMO relaying system with low-resolution analog-to-digital converters (ADCs) at both the relay and destinations. The channel state information (CSI) at the relay is obtained via pilot training, which is then utilized to perform simple maximum-ratio combining/maximum-ratio transmission processing by the relay. Also, it is assumed that the destinations use statistical CSI to decode the transmitted signals. Exact and approximated closed-form expressions for the achievable sum rate are presented, which enable the efficient evaluation of the impact of key system parameters on the system performance. In addition, optimal relay power allocation scheme is studied, and power scaling law is characterized. It is found that, with only low-resolution ADCs at the relay, increasing the number of relay antennas is an effective method to compensate for the rate loss caused by coarse quantization. However, it becomes ineffective to handle the detrimental effect of low-resolution ADCs at the destination. Moreover, it is shown that deploying massive relay antenna arrays can still bring significant power savings, i.e., the transmit power of each source can be cut down proportional to 1/M to maintain a constant rate, where M is the number of relay antennas

Massive MIMO and Full-duplex Relaying Systems

In this thesis, we study how massive multiple-input and multiple-output (MIMO) can be employed to mitigate loop-interference (LI), multi-user interference and noise in a full-duplex (FD) relaying system. For a FD relaying system with massive MIMO deployed at both source and destination, we investigate three FD relaying schemes: co-located, distributed cooperative, and distributed non-cooperative relaying. Asymptotic analysis shows that the three schemes can completely cancel multi-user interference and LI when the number of antennas at the source and destination grows without bound, in the case where the relay has a finite number of antennas. For the system with massive MIMO deployed at the FD relay, we propose a pilot protocol for LI channel minimum-mean-square-error estimation by exploiting the channel coherence time difference between static and moving transceivers. To maximize the end-to-end achievable rate, we design a novel power allocation scheme to adjust the transmit power of each link at the relay in order to equalize the achievable rate of the source-to-relay and relay-to-destination links. The analytical and numerical results show that the proposed pilot protocol and power allocation scheme jointly improve both spectral and energy efficiency significantly. To enable the use of low resolution analog-to-digital converters (ADCs) at relays for energy saving, we propose a novel iterative power allocation scheme to mitigate the resulting quantization noise via reducing the received LI power and numerically identify the optimum resolutions of ADCs for maximizing throughput and energy efficiency. For massive MIMO receivers employing one-bit ADCs, we propose three carrier frequency (CFO) offset estimation schemes for dual-pilot and multiple-pilot cases. The three schemes are developed under different scenarios: large but finite number of antennas at the receiver, infinite number of antennas at the receiver, and very small CFO, respectively

Hardware-Conscious Wireless Communication System Design

The work at hand is a selection of topics in efficient wireless communication system design, with topics logically divided into two groups.One group can be described as hardware designs conscious of their possibilities and limitations. In other words, it is about hardware that chooses its configuration and properties depending on the performance that needs to be delivered and the influence of external factors, with the goal of keeping the energy consumption as low as possible. Design parameters that trade off power with complexity are identified for analog, mixed signal and digital circuits, and implications of these tradeoffs are analyzed in detail. An analog front end and an LDPC channel decoder that adapt their parameters to the environment (e.g. fluctuating power level due to fading) are proposed, and it is analyzed how much power/energy these environment-adaptive structures save compared to non-adaptive designs made for the worst-case scenario. Additionally, the impact of ADC bit resolution on the energy efficiency of a massive MIMO system is examined in detail, with the goal of finding bit resolutions that maximize the energy efficiency under various system setups.In another group of themes, one can recognize systems where the system architect was conscious of fundamental limitations stemming from hardware.Put in another way, in these designs there is no attempt of tweaking or tuning the hardware. On the contrary, system design is performed so as to work around an existing and unchangeable hardware limitation. As a workaround for the problematic centralized topology, a massive MIMO base station based on the daisy chain topology is proposed and a method for signal processing tailored to the daisy chain setup is designed. In another example, a large group of cooperating relays is split into several smaller groups, each cooperatively performing relaying independently of the others. As cooperation consumes resources (such as bandwidth), splitting the system into smaller, independent cooperative parts helps save resources and is again an example of a workaround for an inherent limitation.From the analyses performed in this thesis, promising observations about hardware consciousness can be made. Adapting the structure of a hardware block to the environment can bring massive savings in energy, and simple workarounds prove to perform almost as good as the inherently limited designs, but with the limitation being successfully bypassed. As a general observation, it can be concluded that hardware consciousness pays off

Achievable rates for full-duplex massive MIMO systems with low-resolution ADCs/DACs under imperfect CSI environment

We investigate the uplink and downlink achievable rates of full-duplex (FD) massive multi-input multi-output (MIMO) systems with low-resolution analog-digital converters/digital-to-analog converters (ADCs/DACs), where maximum ratio combining/maximum ratio transmission (MRC/MRT) processing are adopted and imperfect channel state information (CSI) is assumed. In this paper, the quantization noise is encapsulated as an additive quantization noise model (AQNM). Then, employing the minimum mean-square error (MMSE) channel estimator, approximate expressions of the uplink and downlink achievable rates are derived, based on the analysis of the quantization error, loop interference (LI), and the inter-user interference (IUI). It is shown that the interference and noise can be eliminated by applying power scaling law properly and increasing the number of antennas. Moreover, given the number of antennas, it is found that the uplink and downlink approximate achievable rates will converge to a constant when the number of quantization bit tends to infinity. Therefore, the system performance that can be improved by increasing ADC/DAC resolution is limited, implying that it is reasonable to adopt low-resolution ADCs/DACs in FD massive MIMO systems

DOA Estimation for Hybrid Massive MIMO Systems using Mixed-ADCs: Performance Loss and Energy Efficiency

Due to the power consumption and high circuit cost in antenna arrays, the practical application of massive multipleinput multiple-output (MIMO) in the sixth generation (6G) and future wireless networks is still challenging. Employing lowresolution analog-to-digital converters (ADCs) and hybrid analog and digital (HAD) structure is two low-cost choice with acceptable performance loss. In this paper, the combination of the mixedADC architecture and HAD structure employed at receiver is proposed for direction of arrival (DOA) estimation, which will be applied to the beamforming tracking and alignment in 6G. By adopting the additive quantization noise model, the exact closedform expression of the Cramer-Rao lower bound (CRLB) for the HAD architecture with mixed-ADCs is derived. Moreover, the closed-form expression of the performance loss factor is derived as a benchmark. In addition, to take power consumption into account, energy efficiency is also investigated in our paper. The numerical results reveal that the HAD structure with mixedADCs can significantly reduce the power consumption and hardware cost. Furthermore, that architecture is able to achieve a better trade-off between the performance loss and the power consumption. Finally, adopting 2-4 bits of resolution may be a good choice in practical massive MIMO systems.Comment: 11 pages, 7 figure