A 90.5dB DR 1MHz BW Hybrid Two Step ADC with CT Incremental and SAR ADCs

The sensors in real time data processing IoT devices require high resolution and sub-MHz data converters, usually implemented as Incremental ADCs due to the advantages of oversampling technique and low latency. In discrete time incremental (IDT) ADCs, the sampling switch non-linearity, charge injection degrade the resolution, and power hungry OPAMPs are demanded to provide fast and accurate settling for the switch-capacitor circuits. While the continuous time incremental (ICT) ADCs overcome these issues by removing the sampling switches and it also relax the OPAMPs settling accuracy to save power. A hybrid architecture of ICT ADC and SAR two step ADC is proposed to achieve high resolution at low oversampling ratio (OSR). The first ICT ADCs enable higher resolution, faster conversion speed with lower power consumption. The residual error of the ICT ADC is extracted at the last integrator output and transfers to the 2nd SAR for further conversion. In this architecture, only the mismatch between the cascade of integrators (CoIs) and decimation filter transfer functions causes 1st stage quantization noise leakage which can be solved by increasing opamp parameters instead of increasing the digital decimation filter complexity. In addition, the overall SQNR is independent of the first ICT ADC’s NTF, which gives more freedom to trade-off between the loop stability and DAC errors. A 4bits DRZ DAC with data weighted averaging (DWA) technique is adopted to reduce the clock jitter of DAC, mitigate ISI error and static mismatch errors. Based on this architecture, a 16b resolution, 1MHz signal bandwidth hybrid two step ADC is designed and measurement results are demonstrated. Important sub circuits are introduced and analyzed in detail to get the target resolution. The ADC is fabricated in AKM 180nm CMOS process with 1.8V supply voltage, it achieves a DR of 90.5dB, and SNR/SFDR/SNDR of 82.5dB/85dB/80.5dB over 1MHz BW sampled at 64MHz

Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)

Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators

RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs