New Aspects of Fault Diagnosis of Nonlinear Analog Circuits

The paper is focused on nonlinear analog circuits, with the special attention paid to circuits comprising bipolar and MOS transistors manufactured in micrometer and submicrometer technology. The problem of fault diagnosis of this class of circuits is discussed, including locating faulty elements and evaluating their parameters. The paper deals with multiple parametric fault diagnosis using the simulation after test approach as well as detection and location of single catastrophic faults, using the simulation before test approach. The discussed methods are based on diagnostic test, leading to a system of nonlinear algebraic type equations, which are not given in explicit analytical form. An important and new aspect of the fault diagnosis is finding multiple solutions of the test equation, i.e. several sets of the parameters values that meet the test. Another new problems in this area are global fault diagnosis of technological parameters in CMOS circuits fabricated in submicrometer technology and testing the circuits  having multiple DC operating points. To solve these problems several methods have been recently developed, which employ  different concepts and mathematical tools of nonlinear analysis. In this paper they are sketched and illustrated.  All the discussed methods are based on the homotopy (continuation) idea. It is shown that various versions of homotopy and combinations  of the homotopy with some other mathematical algorithms lead to very powerful tools for fault diagnosis of nonlinear analog circuits.  To trace the homotopy path which allows finding multiple solutions, the simplicial method, the restart method, the theory of linear complementarity problem and Lemke's algorithm are employed. For illustration four numerical examples are given

Ultra-small low power temperature-to-digital converter and verification methods of analog circuit with Trojan states

Accurate, small and low-power CMOS temperature sensors designed for multi-position temperature monitoring of power management in multi-core processors are proposed. The temperature sensors utilize the temperature characteristics of the threshold voltage of a MOS transistors to sense temperature and are highly linear from 60°C to 90°C. This is the temperature range needed for the power management applications where temperature sensors are strategically placed at multiple locations in each core to protect the processor from temperature-induced reliability degradation. A temperature-to-digital converter (TDC) that does not require either a reference generator or an ADC is also introduced, and it exhibits low supply sensitivity, small die area, and low power consumption. Both analog threshold voltage based temperature sensor and a prototype TDC designed to support multi-position thermal-sensing for power management applications from 60°C to 90°C are implemented in an IBM 0.13μm CMOS process with a 1.2V power supply. A new verification approach with several variants for identifying the number of stable equilibrium points in supply-insensitive bias generators, references, and temperature sensors based upon self-stabilized feedback loops is introduced. This provides a simple and practical method for determining if these circuits require a “start-up” circuit and, if needed, for verifying that the startup circuit is effective at eliminating undesired stable equilibrium points in the presence of process and temperature variations. These undesired stable equilibrium points are often referred to as Trojan states. It will be shown that some widely used approaches for verification do not guarantee Trojan states have been removed. Some of the methods introduced appear to be more practical to work with than others. A group of benchmark circuit with Trojan states will be introduced and used to demonstrate the effectiveness of the new method

A graphical method for determining the uniqueness of operating points in self-biasing circuits

In self-biasing circuits, designers often use feedbacks to reduce the power-supply sensitivity and minimize the effects of process and temperature variations. Many self-stabilized circuits are used in SOC circuits even when the SOC has a small amount of AMS content. It is well-known that these self-stabilized circuits are vulnerable to not starting-up correctly so start-up circuits are often included to prevent the circuit from getting stuck in an undesired stable operating point. Determining the uniqueness of an operating point in a circuit is challenging since circuit simulators only give a single operating point rather than all operating points. Moreover, this problem is very closely related to the mathematical problem of finding all solutions to a set of nonlinear equations. Both the mathematical and computer science communities recognize this as an open problem with no solution in sight. In circuits with multiple operating points, when a circuit simulator always gives the desired operating point throughout the design and verification process, there is little evidence that one or more undesired operating points even exist. In the semiconductor industry, designers use experience and intuition to identify start-up problems. Some self-stabilized circuits designed by trusted engineers unpredictably get stuck in an undesirable operating point. Engineers often attempt to verify start-up effectiveness with transient simulations. This approach is heuristic and time consuming. Moreover, multiple operating points may still exist in circuits. All circuits we have studied with known need for start-up circuits have a positive feedback loop (PFL) as part of the self-stabilization process. As a result, we made a conjecture that, A circuit is vulnerable to the multiple operating points problem only if the circuit has one or more Positive Feedback Loops. A graphical method for identifying positive feedback loops in analog circuits is presented for the purpose of identifying the stable equilibrium points. Firstly, since our method is based on graphical concepts, some key terminologies from graph theory will be reviewed. Secondly, Graphical models for key analog components are developed and then hierarchically used to obtain a graphical representation of an analog circuit. Thirdly, the concept of determining positive feedback loops from the small-signal resistive Directed, Weighted, Multi-Graph (DWM Graph) of a circuit will be addressed. The three-step process will be used to determine the positive feedback loops. Lastly, a method for breaking positive feedback loop and how to apply the homotopy method to create a return map for the positive feedback loop is introduced. By breaking the positive feedback loop in the circuit and applying break-loop homotopy method, it can determine the uniqueness of operating points in self-biasing circuits. Sample-and-hold circuit is wildly used in mixed-signal circuits such as data converters, filters etc. Thermal noise is often a design limitation in mixed-signal designs. Many literatures and analog textbooks state that the thermal noise voltage sampled on a capacitor is where k is Boltzmann constant, T is temperature and C is capacitance [21][24]. From the expression of thermal noise voltage, we can find that thermal noise is highly related to the capacitor values and independent of resistors. The only way to reduce thermal noise voltage is to increase the capacitance. However, a large capacitor increases the settling time and reduce sampling rate. Meanwhile, layout area and power dissipation will be increased. There is a tradeoff between settling time and accuracy. No literatures introduce a method for reducing thermal noise without increasing capacitance. Reducing noise on a sampling capacitor below may give designers opportunities for improving system performance. A method for reducing thermal noise voltage on a sampling capacitor dramatically below is introduced. In high resolution SAR ADC design, many papers state that the minimum capacitance of capacitor DAC is determined by the thermal noise limitation. This thermal noise limitation is kT/C where k is Boltzmann constant, T is temperature and C is the total capacitance of capacitor DAC. Moreover, they assume this is the input-referred noise for the whole ADC. However, this calculation ignores the noise from charge-redistribution mode completely. Meanwhile, no literatures introduce any method about numerical calculation of thermal noise from charge-redistribution mode of capacitor DAC of SAR ADC. A numerical calculation of thermal noise from charge-redistribution mode of capacitor DAC of SAR ADC is introduced

Hybrid Analog-Digital Co-Processing for Scientific Computation

In the past 10 years computer architecture research has moved to more heterogeneity and less adherence to conventional abstractions. Scientists and engineers hold an unshakable belief that computing holds keys to unlocking humanity's Grand Challenges. Acting on that belief they have looked deeper into computer architecture to find specialized support for their applications. Likewise, computer architects have looked deeper into circuits and devices in search of untapped performance and efficiency. The lines between computer architecture layers---applications, algorithms, architectures, microarchitectures, circuits and devices---have blurred. Against this backdrop, a menagerie of computer architectures are on the horizon, ones that forgo basic assumptions about computer hardware, and require new thinking of how such hardware supports problems and algorithms. This thesis is about revisiting hybrid analog-digital computing in support of diverse modern workloads. Hybrid computing had extensive applications in early computing history, and has been revisited for small-scale applications in embedded systems. But architectural support for using hybrid computing in modern workloads, at scale and with high accuracy solutions, has been lacking. I demonstrate solving a variety of scientific computing problems, including stochastic ODEs, partial differential equations, linear algebra, and nonlinear systems of equations, as case studies in hybrid computing. I solve these problems on a system of multiple prototype analog accelerator chips built by a team at Columbia University. On that team I made contributions toward programming the chips, building the digital interface, and validating the chips' functionality. The analog accelerator chip is intended for use in conjunction with a conventional digital host computer. The appeal and motivation for using an analog accelerator is efficiency and performance, but it comes with limitations in accuracy and problem sizes that we have to work around. The first problem is how to do problems in this unconventional computation model. Scientific computing phrases problems as differential equations and algebraic equations. Differential equations are a continuous view of the world, while algebraic equations are a discrete one. Prior work in analog computing mostly focused on differential equations; algebraic equations played a minor role in prior work in analog computing. The secret to using the analog accelerator to support modern workloads on conventional computers is that these two viewpoints are interchangeable. The algebraic equations that underlie most workloads can be solved as differential equations, and differential equations are naturally solvable in the analog accelerator chip. A hybrid analog-digital computer architecture can focus on solving linear and nonlinear algebra problems to support many workloads. The second problem is how to get accurate solutions using hybrid analog-digital computing. The reason that the analog computation model gives less accurate solutions is it gives up representing numbers as digital binary numbers, and instead uses the full range of analog voltage and current to represent real numbers. Prior work has established that encoding data in analog signals gives an energy efficiency advantage as long as the analog data precision is limited. While the analog accelerator alone may be useful for energy-constrained applications where inputs and outputs are imprecise, we are more interested in using analog in conjunction with digital for precise solutions. This thesis gives novel insight that the trick to do so is to solve nonlinear problems where low-precision guesses are useful for conventional digital algorithms. The third problem is how to solve large problems using hybrid analog-digital computing. The reason the analog computation model can't handle large problems is it gives up step-by-step discrete-time operation, instead allowing variables to evolve smoothly in continuous time. To make that happen the analog accelerator works by chaining hardware for mathematical operations end-to-end. During computation analog data flows through the hardware with no overheads in control logic and memory accesses. The downside is then the needed hardware size grows alongside problem sizes. While scientific computing researchers have for a long time split large problems into smaller subproblems to fit in digital computer constraints, this thesis is a first attempt to consider these divide-and-conquer algorithms as an essential tool in using the analog model of computation. As we enter the post-Moore’s law era of computing, unconventional architectures will offer specialized models of computation that uniquely support specific problem types. Two prominent examples are deep neural networks and quantum computers. Recent trends in computer science research show these unconventional architectures will soon have broad adoption. In this thesis I show another specialized, unconventional architecture is to use analog accelerators to solve problems in scientific computing. Computer architecture researchers will discover other important models of computation in the future. This thesis is an example of the discovery process, implementation, and evaluation of how an unconventional architecture supports specialized workloads

Modellierung, Simulation und Optimierung integrierter Schaltkreise

[no abstract available

Frequency domain steady-state simulation of oscillators

The focus of this work is on developing algorithms for frequency domain steady-state analysis of oscillators. Convergence problems associated with the frequency domain harmonic balance simulation of oscillators have been examined. Globally convergent homotopy methods have been combined with the harmonic balance method for robust high-Q oscillator simulation. Various homotopy options are evaluated leading to an algorithm that is applicable to a wide variety of oscillator circuits. Two new approaches have also been developed for the simulation of ring oscillators using the harmonic balance method. These include a single-delay cell method and a multiple-probe method. The new methods that have been proposed are robust compared to traditional methods and readily converge for a wide range of single-ended and differential oscillators. They enable harmonic balance simulation of “difficult-to-converge” oscillator circuits