Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

One of the primary sources of unpredictability in modern multi-core embedded systems is contention over shared memory resources, such as caches, interconnects, and DRAM. Despite significant achievements in the design and analysis of multi-core systems, there is a need for a theoretical framework that can be used to reason on the worst-case behavior of real-time workload when both processors and memory resources are subject to scheduling decisions. In this paper, we focus our attention on dynamic allocation of main memory bandwidth. In particular, we study how to determine the worst-case response time of tasks spanning through a sequence of time intervals, each with a different bandwidth-to-core assignment. We show that the response time computation can be reduced to a maximization problem over assignment of memory requests to different time intervals, and we provide an efficient way to solve such problem. As a case study, we then demonstrate how our proposed analysis can be used to improve the schedulability of Integrated Modular Avionics systems in the presence of memory-intensive workload.Comment: Accepted for publication in the IEEE Real-Time Systems Symposium (RTSS) 2018 conferenc

Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers

In multicore architectures, there is potential for contention between cores when accessing shared resources, such as system memory. Such contention scenarios are challenging to accurately analyse, from a worst-case timing perspective. One way of making memory contention in multicores more amenable to timing analysis is the use of memory regulation mechanisms. It restricts the number of accesses performed by any given core over time by using periodically replenished per-core budgets. Typically, this assumes that all cores access memory via a single shared memory controller. However, ever-increasing bandwidth requirements have brought about architectures with multiple memory controllers. These control accesses to different memory regions and are potentially shared among all cores. While this presents an opportunity to satisfy bandwidth requirements, existing analysis designed for a single memory controller are no longer safe. This work formulates a worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. This stall analysis can be integrated into the schedulability analysis of systems under fixed-priority partitioned scheduling. Five heuristics for assigning tasks and memory budgets to cores in a stall-cognisant manner are also proposed. We experimentally quantify the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers, and also evaluate the five heuristics for different system characteristics

Neue Implementierungsmethoden für eingebettete geberlose Motor-Controller basierend auf dem Einsatz von Multi-Core-Mikrocontrollern

Diese Arbeit behandelt den Einsatz von Multi-Core-Mikrocontrollern in softwarebasierten Motor-Controllern zur geberlosen Stromregelung von PMSM. Hierbei werden die Steigerung der Motor-Controller-Performance durch Parallelisierung und die Auswirkungen von Cross-Core-Interferenzen auf das zeitliche Verhalten von Motor-Controllern fokussiert. Es wird eine Generalisierung von geberlosen Stromregelungen durchgeführt, um die allgemeine Parallelisierbarkeit dieser Anwendungen zu beschreiben. Hierauf aufbauend wird gezeigt, unter welchen Rahmenbedingungen eine effektive Steigerung der Regelfrequenz durch Parallelisierung realisierbar ist. Durch die Konsolidierung dedizierter Motor-Controller in ein Multi-Core-System kann Hardware eingespart und dadurch der Energiebedarf um bis zu 50 % gesenkt werden. Eine solche Konsolidierung verursacht regelmäßig Cross-Core-Interferenzen. Um diesem Problem entgegenzuwirken, wird ein Verfahren vorgestellt, das die negativen Einflüsse dieser Seiteneffekte auf die Laufzeiten der Motor-Controller analysiert und quantifiziert. Hierauf aufbauend werden Strategien zur Reduktion der Interferenzen beschrieben und evaluiert. Durch die erzielten Ergebnisse werden Multi-Core-Mikrocontroller als Basis neuer Implementierungsmethoden für Motor-Controller erschlossen. Sie erweitern deren Design- und Implementierungsprozesse, um hier Multi-Core-Mikrocontroller durch Parallelisierung und Konsolidierung effektiv und effizient einzusetzen.This thesis addresses the use of multi-core microcontrollers in software-based motor controllers for the position sensorless control of PMSM. The focus is on increasing the motor controller performance through parallelization and on the effects of cross-core interferences on the temporal behaviour of motor controllers. A generalization of position sensorless current controls is carried out in order to describe the general possibilities to parallelize these applications. Building on this, it is shown under which conditions an effective increase in the control frequency can be achieved through parallelization. By consolidating dedicated motor controllers into one multi-core system, hardware can be saved to reduce energy costs by up to 50 %. Such consolidation causes cross-core interference on a regular basis. To address this problem, a procedure is presented that analyses and quantifies the negative influences of these side effects on the runtimes of the motor controllers. Based on this, strategies for reducing interference are described and evaluated. The results of this work open up multi-core microcontrollers as a base for new implementation methods for motor controllers. They expand the design and implementation processes of motor controllers in order to use multi-core microcontrollers effectively and efficiently through parallelization and consolidation