Fast adaptive motion estimation for H.264

H.264 motion estimation achieves better compression efficiency of video coding than previous video standards (e.g. MPEG-2, H.263, and JPEG). But it leads to higher computational cost and complexity in coding. In this study we propose an efficient early termination searching method to reduce the computational complexity and achieve better compression ratio. Adaptive search strategy is applied to reduce the search point in a search range. Furthermore this study presents an analysis of the performance of the proposed algorithm in terms of motion estimation time, total encoding time, and video quality (PSNR). Simulation result shows that compared to Full Search (FS), this algorithm achieves up to 60% reduction in motion estimation time without degrading the video quality

Efficient Motion Field Interpolation Method for Wyner-Ziv Video Coding

Wyner-Ziv video coding has the capability to reduce video encoding complexity by shifting motion estimation procedure from encoder to decoder. Amongst many motion estimation methods, expectation maximization algorithm is the most effective one. Unfortunately, the implementation of block-based motion estimation in this algorithm causes motion field profile bounded by granularity of block size. Nearest-neighbor and bilinear interpolation methods have already applied in multiview image coding to handle similar problem. This paper aims to evaluate performance of both interpolation methods in transform-domain Wyner-Ziv video codec. Results showed that bilinear interpolation effective only for high motion video sequences. In this scenario, it has bitrate saving up to 3.29 %, 0.2 dB higher PSNR, and 12.30 % higher decoding complexity compared to nearest-neighbor. In low motion video content, bitrate saving only gained up to 0.82%, with almost the same PSNR, while decoding complexity increase up to 10.32%. 

Low computational complexity variable block size (VBS) partitioning for motion estimation using the Walsh Hadamard transform (WHT)

Variable Block Size (VBS) based motion estimation has been adapted in state of the art video coding, such as H.264/AVC, VC-1. However, a low complexity H.264/AVC encoder cannot take advantage of VBS due to its power consumption requirements. In this paper, we present a VBS partition algorithm based on a binary motion edge map without either initial motion estimation or Rate-Distortion (R-D) optimization for selecting modes. The proposed algorithm uses the Walsh Hadamard Transform (WHT) to create a binary edge map, which provides a computational complexity cost effectiveness compared to other light segmentation methods typically used to detect the required region

A denoising approach for iterative side information creation in distributed video coding

In distributed video coding, motion estimation is typically performed at the decoder to generate the side information, increasing the decoder complexity while providing low complexity encoding in comparison with predictive video coding. Motion estimation can be performed once to create the side information or several times to refine the side information quality along the decoding process. In this paper, motion estimation is performed at the decoder side to generate multiple side information hypotheses which are adaptively and dynamically combined, whenever additional decoded information is available. The proposed iterative side information creation algorithm is inspired in video denoising filters and requires some statistics of the virtual channel between each side information hypothesis and the original data. With the proposed denoising algorithm for side information creation, a RD performance gain up to 1.2 dB is obtained for the same bitrate

Improved quality block-based low bit rate video coding.

The aim of this research is to develop algorithms for enhancing the subjective quality and coding efficiency of standard block-based video coders. In the past few years, numerous video coding standards based on motion-compensated block-transform structure have been established where block-based motion estimation is used for reducing the correlation between consecutive images and block transform is used for coding the resulting motion-compensated residual images. Due to the use of predictive differential coding and variable length coding techniques, the output data rate exhibits extreme fluctuations. A rate control algorithm is devised for achieving a stable output data rate. This rate control algorithm, which is essentially a bit-rate estimation algorithm, is then employed in a bit-allocation algorithm for improving the visual quality of the coded images, based on some prior knowledge of the images. Block-based hybrid coders achieve high compression ratio mainly due to the employment of a motion estimation and compensation stage in the coding process. The conventional bit-allocation strategy for these coders simply assigns the bits required by the motion vectors and the rest to the residual image. However, at very low bit-rates, this bit-allocation strategy is inadequate as the motion vector bits takes up a considerable portion of the total bit-rate. A rate-constrained selection algorithm is presented where an analysis-by-synthesis approach is used for choosing the best motion vectors in term of resulting bit rate and image quality. This selection algorithm is then implemented for mode selection. A simple algorithm based on the above-mentioned bit-rate estimation algorithm is developed for the latter to reduce the computational complexity. For very low bit-rate applications, it is well-known that block-based coders suffer from blocking artifacts. A coding mode is presented for reducing these annoying artifacts by coding a down-sampled version of the residual image with a smaller quantisation step size. Its applications for adaptive source/channel coding and for coding fast changing sequences are examined

A High permormance hardware architecture for an sad reuse based hierarchical motion estimation algorithm for H.264 video coding

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of an SAD reuse based hierarchical motion estimation algorithm for H.264 / MPEG4 Part 10 video coding. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 68 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640x480) or 82 CIF frames (352x288) per second

Fast block matching motion estimation algorithms for video compression

As the telecommunication technology grows in the modern era from internet to video conferencing, Video compression has become an avoidable feature in information broadcast and also in the entertainment media. In this thesis we compared a different block matching motion estimation algorithms to find the motion estimation with a rapid growth of multimedia information; when transmitting a large amount of data video coding standards have become crucial. Motion estimation ascertain to be the key to splendid performance in video coding by recover the temporal redundancy effectively between adjacent frames, so it has been widely used to popular video compression coding standards such as MPEG-2, MPEG-4 and recent video coding standards H.264 of video data for storage and transmission. So Based on the study of motion vector distribution from several commonly used test image sequences, a three step diamond search [TSDS]algorithm for fast block matching motion estimation is proposed in this paper .The performance of this algorithm is compared with other existing algorithms of basic full search [FS], three step search [TSS] and diamond search [DS] by means of error metrics and no of search points in this the simulation results shows that the proposed three step diamond search algorithm achieves close performance with that of diamond search [DS] and uses less no of search points than the three step search[TSS]. When compared with original diamond search [DS] algorithm, this algorithm requires less computation time and gives an improved performance