Modeling, Fabrication, and Optimization of Niobium Cavities: Phase II Final Report

Niobium cavities are important parts of the integrated NC/SC high-power linacs. Over the years, researchers in several countries have tested various cavity shapes. They concluded that elliptically shaped cells are the most appropriate shape for superconducting cavities. The need for very clean surfaces lead to the use of a buffered chemical polishing produce for surface cleaning to get good performance of the cavities. The second phase has resulted in an experimental setup of a fluid flow experiment with experimentation to be completed in the third year. Some of these results were presented at American Nuclear Society, Student Conference April 2-5, 2003. Other experimental activities include the evaluation of a vacuum system and various vacuum equipment purchases and modifications. An optimization code for a five-cell niobium cavity based on resonant frequency and mode number was developed and presented at the 2003 ANS conference in San Diego

Scaling NbTiN-based ac-powered Josephson digital to 400M devices/cm2^2

We describe a fabrication stackup for digital logic with 16 superconducting NbTiN layers, self-shunted a-silicon barrier Josephson Junctions (JJs), and low loss, high-$\kappa$ tunable HZO capacitors. The stack enables 400 MJJ/cm$^2$ device density, efficient routing, and AC power distribution on a resonant network. The materials scale beyond 28nm lithography and are compatible with standard high-temperature CMOS processes. We report initial results for two-metal layer NbTiN wires with 50nm critical dimension. A semi-ascendance wire-and-via process module using 193i lithography and 50nm critical dimension has shown cross-section uniformity of 1%=1s across the 300mm wafer, critical temperature of 12.5K, and critical current of 0.1mA at 4.2K. We also present a new design of the resonant AC power network enabled by NbTiN wires and HZO MIM capacitors. The design matches the device density and provides a 30 GHz clock with estimated efficiency of up to 90%. Finally, magnetic imaging of patterned NbTiN ground planes shows low intrinsic defectivity and consistent trapping of vorteces in 0.5 mm holes spaced on a 20 $\mu$m x 20 $\mu$m grid.Comment: 7 pages, 3 figure

Signal and power integrity co-simulation using the multi-layer finite difference method

Mixed signal system-on-package (SoP) technology is a key enabler for increasing functional integration, especially in mobile and wireless systems. Due to the presence of multiple dissimilar modules, each having unique power supply requirements, the design of the power distribution network (PDN) becomes critical. Typically, this PDN is designed as alternating layers of power and ground planes with signal interconnects routed in between or on top of the planes. The goal for the simulation of multi-layer power/ground planes, is the following: Given a stack-up and other geometrical information, it is required to find the network parameters (S/Y/Z) between port locations. Commercial packages have extremely complicated stack-ups, and the trend to increasing integration at the package level only points to increasing complexity. It is computationally intractable to solve these problems using these existing methods. The approach proposed in this thesis for obtaining the response of the PDN is the multi-layer finite difference method (M-FDM). A surface mesh / finite difference based approach is developed, which leads to a system matrix that is sparse and banded, and can be solved efficiently. The contributions of this research are the following: 1. The development of a PDN modeler for multi-layer packages and boards called the the multi-layer finite difference method. 2. The enhancement of M-FDM using multi-port connection networks to include the effect of fringe fields and gap coupling. 3. An adaptive triangular mesh based scheme called the multi-layer finite element method (MFEM) to address the limitations of M-FDM 4. The use of modal decomposition for the co-simulation of signal nets with the PDN. 5. The use of a robust GA-based optimizer for the selection and placement of decoupling capacitors in multi-layer geometries. 6. Implementation of these methods in a tool called MSDT 1.Ph.D.Committee Chair: Madhavan Swaminathan; Committee Member: Andrew F. Peterson; Committee Member: David C. Keezer; Committee Member: Saibal Mukhopadyay; Committee Member: Suresh Sitarama

Energy-Efficient Neural Network Architectures

Emerging systems for artificial intelligence (AI) are expected to rely on deep neural networks (DNNs) to achieve high accuracy for a broad variety of applications, including computer vision, robotics, and speech recognition. Due to the rapid growth of network size and depth, however, DNNs typically result in high computational costs and introduce considerable power and performance overheads. Dedicated chip architectures that implement DNNs with high energy efficiency are essential for adding intelligence to interactive edge devices, enabling them to complete increasingly sophisticated tasks by extending battery lie. They are also vital for improving performance in cloud servers that support demanding AI computations. This dissertation focuses on architectures and circuit technologies for designing energy-efficient neural network accelerators. First, a deep-learning processor is presented for achieving ultra-low power operation. Using a heterogeneous architecture that includes a low-power always-on front-end and a selectively-enabled high-performance back-end, the processor dynamically adjusts computational resources at runtime to support conditional execution in neural networks and meet performance targets with increased energy efficiency. Featuring a reconfigurable datapath and a memory architecture optimized for energy efficiency, the processor supports multilevel dynamic activation of neural network segments, performing object detection tasks with 5.3x lower energy consumption in comparison with a static execution baseline. Fabricated in 40nm CMOS, the processor test-chip dissipates 0.23mW at 5.3 fps. It demonstrates energy scalability up to 28.6 TOPS/W and can be configured to run a variety of workloads, including severely power-constrained ones such as always-on monitoring in mobile applications. To further improve the energy efficiency of the proposed heterogeneous architecture, a new charge-recovery logic family, called zero-short-circuit current (ZSCC) logic, is proposed to decrease the power consumption of the always-on front-end. By relying on dedicated circuit topologies and a four-phase clocking scheme, ZSCC operates with significantly reduced short-circuit currents, realizing order-of-magnitude power savings at relatively low clock frequencies (in the order of a few MHz). The efficiency and applicability of ZSCC is demonstrated through an ANSI S1.11 1/3 octave filter bank chip for binaural hearing aids with two microphones per ear. Fabricated in a 65nm CMOS process, this charge-recovery chip consumes 13.8µW with a 1.75MHz clock frequency, achieving 9.7x power reduction per input in comparison with a 40nm monophonic single-input chip that represents the published state of the art. The ability of ZSCC to further increase the energy efficiency of the heterogeneous neural network architecture is demonstrated through the design and evaluation of a ZSCC-based front-end. Simulation results show 17x power reduction compared with a conventional static CMOS implementation of the same architecture.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147614/1/hsiwu_1.pd

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

High-clock skew variations and degradation of driving ability of buffers lead to an additional power dissipation in Clock Distribution Network (CDN) that increases the dimensionality of buffers and coordination among flip-flops. The manual threshold level to predict the Region of Interest (ROI) is not applicable in clustering process due to the complexities of excessive wire length and critical delay. This paper proposes the Distance and Load Weight Updated Clustering (DLWUC) to determine the suitable position of logical components. Initially, the DLWUC utilizes the Hybrid Weighted Distance (HWD) to estimate the distance and construct the distance matrix. The weight value extracted from the sorted distance matrix facilitates the projection of buffers. The updated weight value serves as the base for clustering with labeled outputs. The placement of buffer at the suitable place from load weight updated clustering provides the necessary trade-off between clock provision and load balance. The DLWUC discussed in this paper reduces the size of buffers, skew, power and latency compared to the existing topologies

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling

With the advent of many-core chips that place substantial demand on the NoC, photonics has been investigated as a promising alternative to electrical NoCs. While numerous opto-electronic NoCs have been proposed, their evaluations tend to be based on fixed numbers for both photonic and electrical components, making it difficult to co-optimize. Through our own forays into opto-electronic NoC design, we observe that photonics and electronics are very much intertwined, reflecting a strong need for a NoC modeling tool that accurately models parameterized electronic and photonic components within a unified framework, capturing their interactions faithfully. In this paper, we present a tool, DSENT, for design space exploration of electrical and opto-electrical networks. We form a framework that constructs basic NoC building blocks from electrical and photonic technology parameters. To demonstrate potential use cases, we perform a network case study illustrating data-rate tradeoffs, a comparison with scaled electrical technology, and sensitivity to photonics parameters

DESIGN, MODELING AND CHARACTERIZATION OF A PIEZOELECTRIC ENERGY HARVESTING DEVICE

The mechanical vibratory energy has been extracted based on the car engine’s frequency and converted into an electrical energy by making use of a bimorph piezoelectric harvesting device; this process is called energy harvesting. The output of that energy used to power-up small electronics devices such as electronic transmitters and sensors which utilize low voltage and current (1-5 Volt / 10 - 20 mA). A cantilever of Lead-Zirconate-Titanate (PbZrO3TiO2) with dimensions of (40 × 10 × 0.5 mm) has been analyzed and it’s produced an output power in the range of (100μW - 0.4mW) at resonance frequency of (≤ 0.2 KHz) under peak acceleration of (≤ 10 m/s2). This cantilever’s targeted vibration is dynamic (damped) vibration; therefore it has been subjected into continuous vibratory force. The Static Vibration is run at the first stages to check the working force and stamina of the cantilever by applying a pulse of movement and observe the response of the transient wave of the cantilever. The project aims to design and model a bimorph piezoelectric (PZT) cantilever device uses the effects of piezoelectric property to extract the mechanical vibration that is generated based on the car engine compartment’s specifications and convert it to electrical energy. Successfully, a bimorph piezoelectric harvester cantilever was designed under the optimal conditions identified in this report to extract the car engine vibration produced by dynamic vibration shaker using the typical frequencies and acceleration of the car engine and produced output power nearly 0.39 mW when converts this extracted vibration to electrical energ

Investigation of the power-clock network impact on adiabatic logic

International audienceAdiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the power-clock network still remains to be studied. In this paper, we investigate the power-clock network effect on adiabatic energy dissipation. We derive closed-form analytical formulas to represent the output signal voltage and energy dissipation while taking into account the parasitic impedance of the power-clock network with respect to switching frequency such that adiabatic conditions are still met. Experiments, based on simulation, show that the power-clock network impacts both the energy efficiency of the circuit and its frequency