Impact of Hot Carrier Aging on Random Telegraph Noise and Within a Device Fluctuation

For nanometer MOSFETs, charging and discharging a single trap induces random telegraph noise (RTN). When there are more than a few traps, RTN signal becomes complex and appears as within a device fluctuation (WDF). RTN/WDF causes jitters in switch timing and is a major challenge to low power circuits. In addition to RTN/WDF, devices also age. The interaction between RTN/WDF and aging is of importance and not fully understood. Some researchers reported aging increasing RTN/WDF, while others showed RTN/WDF being hardly affected by aging. The objective of this work is to investigate the impact of hot carrier aging (HCA) on the RTN/WDF of nMOSFETs. For devices of average RTN/WDF, it is found that the effect of HCA is generally modest. For devices of abnormally high RTN/WDF, however, for the first time, we report HCA reducing RTN/WDF substantially (>50%). This reduction originates from either a change of current distribution or defect losses

Impact of Hot Carrier Aging on Random Telegraph Noise and Within a Device Fluctuation

For nanometer MOSFETs, charging and discharging a single trap induces random telegraph noise (RTN). When there are more than a few traps, RTN signal becomes complex and appears as within a device fluctuation (WDF). RTN/WDF causes jitters in switch timing and is a major challenge to low power circuits. In addition to RTN/WDF, devices also age. The interaction between RTN/WDF and aging is of importance and not fully understood. Some researchers reported aging increasing RTN/WDF, while others showed RTN/WDF being hardly affected by aging. The objective of this work is to investigate the impact of hot carrier aging (HCA) on the RTN/WDF of nMOSFETs. For devices of average RTN/WDF, it is found that the effect of HCA is generally modest. For devices of abnormally high RTN/WDF, however, for the first time, we report HCA reducing RTN/WDF substantially (>50%). This reduction originates from either a change of current distribution or defect losses

MODELING OF HOT-CARRIER DEGRADATION BASED ON THOROUGH CARRIER TRANSPORT TREATMENT

We present and validate a physics-basedmodel for hot-carrier degradation. The model is based on a thorough carrier transport treatment by means of an exact solution of the Boltzmann transport equation. Such important ingredients relevant for hot-carrier degradation as the competing mechanisms of bond dissociation, electron-electron scattering, the activation energy reduction due to the interaction of the dipole moment of the bond with the electric field as well as statistical fluctuations of this energy are incorporated in our approach. The model is validated in order to represent the linear drain current change in three different devices subjected to hot-carrier stress under different conditions. The main demand is that the model has to use a unique set of parameters. We analyze the importance of all the model ingredients, especially the role of electron-electron scattering. We check the idea that the channel/gate length ofthe device alone is not enough to judge whether electron-electron scattering is important or not and instead a combination of the device topology and stress conditions needs to be used

Insight into Electron Traps and Their Energy Distribution under Positive Bias Temperature Stress and Hot Carrier Aging

The access transistor of SRAM can suffer both Positive Bias Temperature Instability (PBTI) and Hot Carrier Aging (HCA) during operation. The understanding of electron traps (ETs) is still incomplete and there is little information on their similarity and differences under these two stress modes. The key objective of this paper is to investigate ETs in terms of energy distribution, charging and discharging properties, and generation. We found that both PBTI and HCA can charge ETs which center at 1.4eV below conduction band (Ec) of high-k (HK) dielectric, agreeing with theoretical calculation. For the first time, clear evidences are presented that HCA generates new ETs, which do not exist when stressed by PBTI. When charged, the generated ETs’ peak is 0.2eV deeper than that of pre-existing ETs. In contrast with the power law kinetics for charging the pre-existing ETs, filling the generated ETs saturates in seconds, even under an operation bias of 0.9 V. ET generation shortens device lifetime and must be included in modelling HCA. A cyclic and anti-neutralization ETs model (CAM) is proposed to explain PBTI and HCA degradation, which consists of pre-existing cyclic electron traps (PCET), generated cyclic electron traps (GCET), and anti-neutralization electron traps (ANET)

Reliability of deep submicron MOSFETs, Journal of Telecommunications and Information Technology, 2001, nr 1

In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature is given. The main hot carrier effects and degradations are compared for bulk and SOI devices in a wide range of gate length, down to deep submicron. The worst case aging, device lifetime and maximum drain bias that can be applied are addressed. The physical mechanisms and the emergence of new phenomena at the origin of the degradation are studied for advanced MOS transistors. The impact of the substrate bias is also outlined

Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With GeO2/Al2O3 Stack

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with Ge/GeO2/Al2O3 stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the timeexponent varies with stress biases/field when measured by either the conventional slow dc or pulse I–V technique, making the conventional Vg-accelerated method for predicting the lifetime of Si pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in Ge/GeO2/Al2O3 can be fully annealed at 150 °C; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., Ev, when neutral, lift well above Ev after charging, and return below Ev following neutralization

Threshold voltage instabilities in MOS transistors with advanced gate dielectrics

Ph.DDOCTOR OF PHILOSOPH

DEFECTS AND LIFETIME PREDICTION OF GERMANIUM MOSFETS

To continue improving device speed, much effort has been made to replace Si by high mobility semiconductors. Ge is considered as a strong candidate for pMOSFETs due to the high hole mobility. Two approaches have been demonstrated: high-k/Si-cap/Ge and high-k/GeO2/Ge. Negative Bias Temperature Instability (NBTI) is still one of the main reliability issues, limiting the device lifetime. In this project, it is found that the conventional lifetime prediction method developed for Si is inapplicable to Ge devicesand defect properties in Ge and Si MOSFETs are different.The threshold voltage degradation in Ge can be nearly 100% recovered under a much lower temperature than that in Si devices. The defect losses observed in Si devices were absent in Ge/GeO2/Al2O3. The generation of interface states is insignificant and the positive charges in GeO2/Al2O3 on Ge dominate the NBTI. These positive charges do not follow the same model as those in SiON/Si and an energy-alternating model has been proposed: there are a spread of energy levels of neutral hole traps below Ev andthey lift up after charging, and return below Ev after neutralization.The energy distribution of positive charges in the Al2O3/GeO2/Ge gate stack was studied by the Discharge-based Multi-pulse (DMP) Technique. The different stress-time dependence of defects below Ev and around Ec indicates that they originate from different defects. Quantization effect, Fermi level pinning, and discharge voltage step were considered. The defect differences in terms of the energy level were investigated by using the DMP technique and the energy alternating model is verified by the defect energy distribution.Based on the understanding of different defect behavior, a new NBTI lifetime prediction method was developed for Ge MOSFETs. Energy alternating defects were separated from as-grown hole traps (AHT), which enables to restore the power law for NBTI kinetics with a constant power exponent. The newly developed Ge method was applicable for NBTI lifetime prediction of the state-of-the-art Si-cap/Ge and GeO2/Ge MOSFETs. When compared with SiON/Si, the optimized Si-cap/Ge shows superior reliability, while GeO2/Ge is inferior and needs further optimization. Preliminary characterization was also carried out to investigate the impacts of energy levels and characteristic times of different defects on the frequency and duty factor dependence of AC NBTI degradation

Journal of Telecommunications and Information Technology, 2007, nr 2

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