Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Additivity of Capacitive and Inductive Coupling in Submicronic Interconnects

International audienceConstant evolution in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. Inductive coupling effects on interconnects is an emerging concern in high performance digital integrated circuits. Based on an RLC transmission line model, associated to each propagation mode, a new crosstalk noise model is proposed to evaluate both the capacitive and the inductive coupling. The additivity of the coupling is shown and validated with several simulations

Analysis of crosstalk and field coupling to lossy MTL's in a SPICE environment

This paper proposes a circuit model for lossy multiconductor transmission lines (MTLs) suitable for implementation in modern SPICE simulators, as well as in any simulator supporting differential operators. The model includes the effects of a uniform or nonuniform disturbing field illuminating the line and is especially devised for the transient simulation of electrically long wideband interconnects with frequency dependent per-unit-length parameters. The MTL is characterized by its transient matched scattering responses, which are computed including both dc and skin losses by means of a specific algorithm for the inversion of the Laplace transform. The line characteristics are then represented in terms of differential operators and ideal delays to improve the numerical efficiency and to simplify the coding of the model in existing simulators. The model can be successfully applied to many kinds of interconnects ranging from micrometric high-resistivity metallizations to low-loss PCBs and cables, and can be considered a practical extension of the widely appreciated lossless MTL SPICE model, which maintains the simplicity and efficienc

Crosstalk analysis of carbon nanotube bundle interconnects

Carbon nanotube (CNT) has been considered as an ideal interconnect material for replacing copper for future nanoscale IC technology due to its outstanding current carrying capability, thermal conductivity, and mechanical robustness. In this paper, crosstalk problems for single-walled carbon nanotube (SWCNT) bundle interconnects are investigated; the interconnect parameters for SWCNT bundle are calculated first, and then the equivalent circuit has been developed to perform the crosstalk analysis. Based on the simulation results using SPICE simulator, the voltage of the crosstalk-induced glitch can be reduced by decreasing the line length, increasing the spacing between adjacent lines, or increasing the diameter of SWCNT

Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

Analysis of Crosstalk Noise for 2π RC Model considering Interconnect Parameters in Deep Submicron VLSI Circuit

As the technology enters into deep sub-micron region, signal integrity is becoming a very crucial parameter. In order to deal with the challenges associated with signal integrity problem, such as, crosstalk noise and delay, estimation and minimizing techniques should be addressed with great importance. Along with this, the peak noise amplitude and noise width values in the sensitive node must be verified and confirmed that they are below the certain threshold levels. Hence, for a particular range of frequency, an accurate and efficient crosstalk noise estimation model is necessary to confirm the signal integrity. Therefore, this work aims to analyse the crosstalk noise between two interconnect lines using 2π RC model, and considering its physical parameters, such as the parasitic capacitance, resistance and inductance and interconnect parameters, specifically the spacing between two interconnects, length, width, thickness, height from substrate in deep sub-micron VLSI circuit. In this paper, analytical expressions for peak noise amplitude and noise width in 2π model with RC interconnects for unit step input were derived, and then it was simulated in MATLAB and HSPICE software platform. The MATLAB based results represent that 2π model possesses less errors, and showed better performance compared to some other popular models by adjusting the interconnecting parameters for any certain range of operating frequency. The HSPICE simulation justifies the accuracy of the approach with full satisfaction