Model order reduction of time-delay systems using a laguerre expansion technique

The demands for miniature sized circuits with higher operating speeds have increased the complexity of the circuit, while at high frequencies it is known that effects such as crosstalk, attenuation and delay can have adverse effects on signal integrity. To capture these high speed effects a very large number of system equations is normally required and hence model order reduction techniques are required to make the simulation of the circuits computationally feasible. This paper proposes a higher order Krylov subspace algorithm for model order reduction of time-delay systems based on a Laguerre expansion technique. The proposed technique consists of three sections i.e., first the delays are approximated using the recursive relation of Laguerre polynomials, then in the second part, the reduced order is estimated for the time-delay system using a delay truncation in the Laguerre domain and in the third part, a higher order Krylov technique using Laguerre expansion is computed for obtaining the reduced order time-delay system. The proposed technique is validated by means of real world numerical examples

Matrix-interpolation-based parametric model order reduction for multiconductor transmission lines with delays

A novel parametric model order reduction technique based on matrix interpolation for multiconductor transmission lines (MTLs) with delays having design parameter variations is proposed in this brief. Matrix interpolation overcomes the oversize problem caused by input-output system-level interpolation-based parametric macromodels. The reduced state-space matrices are obtained using a higher-order Krylov subspace-based model order reduction technique, which is more efficient in comparison to the Gramian-based parametric modeling in which the projection matrix is computed using a Cholesky factorization. The design space is divided into cells, and then the Krylov subspaces computed for each cell are merged and then truncated using an adaptive truncation algorithm with respect to their singular values to obtain a compact common projection matrix. The resulting reduced-order state-space matrices and the delays are interpolated using positive interpolation schemes, making it computationally cheap and accurate for repeated system evaluations under different design parameter settings. The proposed technique is successfully applied to RLC (R-resistor, L-inductor, C-capacitance) and MTL circuits with delays

Modeling for the Computer-Aided Design of Long Interconnects

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