Formal Verification of Tokeneer Behaviours Modelled in fUML Using CSP

Much research work has been done on formalizing UML diagrams, but less has focused on using this formalization to analyze the dynamic behaviours between formalized components. In this paper we propose using a subset of fUML (Foundational Subset for Executable UML) as a semi-formal language, and formalizing it to the process algebraic specification language CSP, to make use of FDR as a model checker. Our formalization includes modelling the asynchronous communication framework used within fUML. This allows different interpretations of the communications model to be evaluated. To illustrate the approach, we use the modelling of the Tokeneer ID Station specifications into fUML, and formalize them in CSP to check if the model is deadlock free

On Detecting Concurrency Defects Automatically at the Design Level

We describe an automated approach for detecting concurrency defects from design diagrams of a software, in particular, sequence diagrams. From a given sequence diagram, we automatically infer a formal, parallel specification that generalizes the communication behavior that is designed informally and incompletely in the diagram. We model-check the parallel specification against generic concurrency defect patterns. No additional specification of the software is needed. We present several case-studies to evaluate our approach. The results show that our approach is technically feasible, and effective in detecting nasty concurrency defects at the design level

Pengembangan Kakas Bantu Pembangkitan Kasus Uji pada Model-Based Testing Berdasarkan Activity Diagram

gan perangkat lunak. Kompleksitas dalam pengujian sistem menyebabkan kebutuhan akan kakas bantu yang dapat menentukan kasus uji secara otomatis. Activity diagram merupakan salah satu UML behavioural model yang cocok untuk pengujian sistem, karena activity diagram dapat menggambarkan alur dari sebuah sistem secara keseluruhan. Oleh karena itu penelitian ini dimaksudkan untuk mengambangkan suatu kakas bantu pembangkitan yang dapat menentukan kasus uji pada model based testing berdasarkan activity diagram secara otomatis . Teknik yang dipakai dalam pembangkitan kasus uji dengan membangun sebuah dependency flow tree (DFT) yang menampung informasi dari file activity diagram ArgoUML melalui bantuan sebuah parser. Kemudian DFT tersebut diproses dengan sebuah algoritme depth first search (DFS) yang sudah dimodifikasi untuk menelusuri setiap jalur dari kasus uji. Dalam pengembangan kakas bantu penulis menggunakan software development life cycle (SDLC) waterfall model. Seluruh kebutuhan dari kakas bantu merupakan hasil elisitasi kebutuhan pada kajian pustaka pada penelitian terkait dan observasi pada beberapa website kakas bantu perangkat lunak. Selanjutnya penulis melakukan perancangan yang terdiri dari perancangan arsitektur, perancangan algoritme dan perancangan antar muka. Implementasi kakas bantu menggunakan bahasa PHP dengan framework laravel versi 5.8. Kakas bantu ini telah diuji melalui beberapa tahapan. Pengujian unit menggunakan metode white box dengan teknik basis path testing. Pengujian integrasi antar unit menggunakan pendekatan big-bang. Pengujian validasi dengan metode black-box. Kasus uji yang dihasilkan memiliki tingkat akurasi 100%

Uma nova abordagem para geração automática de propriedades para verificação formal de sistemas digitais em HDL

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Ciência da Computação, Florianópolis, 2013.A flexibilidade de FPGAs baseadas em SRAM é uma opção atrativa para o projeto de sistemas embarcados. Contudo, estes sistemas críticos requerem a verificação funcional do projeto em HDL (Hardware Description Language) para assegurar o seu correto funcionamento. A verificação formal utilizando model checking representa um sistema em um modelo formal que pode ser automaticamente gerado por ferramentas de síntese. No entanto, as propriedades que descrevem o comportamento esperado, necessárias para provadores de modelo, são usualmente elaboradas de forma manual, o que é mais suscetível a erro humano, aumentando custo e tempo de verificação. Este trabalho apresenta uma nova abordagem para geração automática de propriedades para verificação de sistemas descritos em HDL. O estudo de caso industrial é o subsistema de comunicação de um satélite artificial que foi desenvolvido em parceria com o Instituto Nacional de Pesquisas Espaciais (INPE).Abstract: The flexibility of Commercial-Off-The-Shelf (COTS) SRAM-based FPGAs is an attractive option for the design of embedded systems. However, the functional verification of HDL-based designs is required and is of fundamental importance. Formal verification using model checking represents a system as formal model that are automatically generated by synthesis tools. On the other hand, the properties are represented by temporal logic expressions and are traditionally elaborated by hand, which is susceptible to human errors thus increasing the costs and verification time. This work presents a new method for automatic property generation for formal verification of Hardware Description Language (HDL) based systems. The industrial case study is a communication subsystem of an artificial satellite, which was developed in cooperation with the Brazilian Institute of Space Research (INPE)