Wireless Channel Modeling For Networks On Chips

The advent of integrated circuit (chip) multiprocessors (CMPs) combined with the continuous reduction in device physical size (technology scaling) to the sub-nanometer regime will result in an exponential increase in the number of processing cores that can be integrated within a single chip. Today’s CMPs already support tens to low hundreds of cores and both industry and academic roadmaps project that future chips will have thousands of cores. Therefore, while there are open questions on how to harness the computing power offered by CMPs, the design of power-efficient and compact on-chip interconnection networks that connects cores, caches and memory controllers has become imperative for sustaining the performance of CMPs. As the limited scalability of bus-based networks degrades performance by reducing data rates and increasing latency, the Network-on-Chip (NoC) design paradigm has gained momentum, where a network of routers and links connects all the cores. However, power consumption of NoCs is a significant challenge that should be addressed to capitalize on the scaling advantages of multicores. Also, improvements in metal wire characteristics will no longer satisfy the power and performance requirements of on-chip communication. One approach to continue the performance improvements is to integrate new emerging technologies into the electronic design flow such as wireless/RF technologies, since they provide unique advantages that make them desirable in a NoC environment. First, wireless technologies are ubiquitous and offer a wide range of options in communication, and there exists a vast body of knowledge for the design and implementation of wireless chipsets using RF-CMOS technology. Second, wireless communication, unlike wired transmission, can be omnidirectional, which can facilitate one-hop unicast, multicast, and broadcast communication that can result in a reduction in power consumption while allowing for faster communication. Third, wireless communication can increase the communication data rate by the combination of Frequency Division Multiplexing (FDM) and Time Division Multiplexing (TDM) (and in the future, potentially spatial division multiplexing (SDM)). Therefore, Wireless NoC (WiNoC) interconnects have recently emerged as a viable solution to mitigate power concerns in the short to medium term while still providing competitive performance metrics, i.e., low power consumption, tens of Gbps data rates, and minimal circuit area (or volume) within the chip. Worth noting is that wireless links are not envisioned as replacing all wired links, but rather as augmenting the wired interconnection network. In this dissertation, we employ simulations in HFSS from Ansys® to present accurate wireless channel models for a realistic WiNoC environment. We investigate the performance of these models with different types of narrowband and wideband antennas. This entails estimation of the scattering parameters for the channels between multiple antenna elements in the WiNoC, from which we derive channel transfer functions and channel impulse responses. Using these results, we can estimate the throughput of the various WiNoC links, and this allows us to design effective multiple access (MA) schemes via FDM and TDM. For these MA schemes, we provide estimates of maximal throughput. To further the feasibility study, we investigate the performance of a simple binary transmission scheme--On-Off Keying (OOK)--through the resulting dispersive channels, which can facilitate one-hop unicast, multicast, and broadcast communication that can result in a reduction in power consumption while allowing for faster communication. Our investigation of the performance of On-Off Keying modulation (OOK) also includes an analytical expression for bit error ratio (BER) that can be evaluated numerically. This enables us to provide the equalization requirements needed to achieve our target BERs. Finally, we provide recommendations for WiNoC design and future tasks related to this research

ReSCon '09, Research Student Conference: Book of Abstracts

The second SED Research Student Conference (ReSCon2009) was hosted over three days, 22-24 June 2009, in the Lecture Centre at Brunel University. The conference consisted of technical presentations, a poster session and social events. The abstracts and presentations were the result of ongoing research by postgraduate research students from the School of Engineering and Design at Brunel University. The conference is held annually, and ReSCon plays a key role in contributing to research and innovations within the School

Towards the Design of Robust High-Speed and Power Efficient Short Reach Photonic Links

In 2014, approximately eight trillion transistors were fabricated every second thanks to improvements in integration density and fabrication processes. This increase in integration and functionality has also brought about the possibility of system on chip (SoC) and high-performance computing (HPC). Electrical interconnects presently dominate the very-short reach interconnect landscape (< 5 cm) in these applications. This, however, is expected to change. These interconnects' downfall will be caused by their need for impedance matching, limited pin-density and frequency dependent loss leading to intersymbol interference. In an attempt to solve this, researchers have increasingly explored integrated silicon photonics as it is compatible with current CMOS processes and creates many possibilities for short-reach applications. Many see optical interconnects as the high-speed link solution for applications ranging from intra-data center (~200 m) down to module or even chip scales (< 2 cm). The attractive properties of optical interconnects, such as low loss and multiplexing abilities, will enable such things as Exascale high-performance computers of the future (equal to 10^18 calculations per second). In fact, forecasts predict that by 2025 photonics at the smallest levels of the interconnect hierarchy will be a reality. This thesis presents three novel research projects, which all work towards increasing robustness and cost-efficiency in short-reach optical links. It discusses three parts of the optical link: the interconnect, the receiver and the photodiode. The first topic of this thesis is exploratory work on the use of an optical multiplexing technique, mode-division multiplexing (MDM), to carry multiple data lanes along with a forwarded clock for very short-reach applications. The second topic discussed is a novel reconfigurable CMOS receiver proposed as a method to map a clock signal to an interconnect lane in an MDM source-synchronous link with the lowest optical crosstalk. The receiver is designed as a method to make electronic chips that suit the needs of optical ones. By leveraging the more robust electronic integrated circuit, link solutions can be tuned to meet the needs of photonic chips on a die by die basis. The third topic of this thesis proposes a novel photodetector which uses photonic grating couplers to redirect vertical incident light to the horizontal direction. With this technique, the light is applied along the entire length of a p-n junction to improve the responsivity and speed of the device. Experimental results for this photodetector at 35 Gb/s are published, showing it to be the fastest all-silicon based photodetector reported in the literature at the time of publication

Goddard Conference on Mass Storage Systems and Technologies, volume 2

Papers and viewgraphs from the conference are presented. Discussion topics include the IEEE Mass Storage System Reference Model, data archiving standards, high-performance storage devices, magnetic and magneto-optic storage systems, magnetic and optical recording technologies, high-performance helical scan recording systems, and low end helical scan tape drives. Additional discussion topics addressed the evolution of the identifiable unit for processing (file, granule, data set, or some similar object) as data ingestion rates increase dramatically, and the present state of the art in mass storage technology

CEPC Technical Design Report -- Accelerator (v2)

The Circular Electron Positron Collider (CEPC) is a large scientific project initiated and hosted by China, fostered through extensive collaboration with international partners. The complex comprises four accelerators: a 30 GeV Linac, a 1.1 GeV Damping Ring, a Booster capable of achieving energies up to 180 GeV, and a Collider operating at varying energy modes (Z, W, H, and ttbar). The Linac and Damping Ring are situated on the surface, while the Booster and Collider are housed in a 100 km circumference underground tunnel, strategically accommodating future expansion with provisions for a Super Proton Proton Collider (SPPC). The CEPC primarily serves as a Higgs factory. In its baseline design with synchrotron radiation (SR) power of 30 MW per beam, it can achieve a luminosity of 5e34 /cm^2/s^1, resulting in an integrated luminosity of 13 /ab for two interaction points over a decade, producing 2.6 million Higgs bosons. Increasing the SR power to 50 MW per beam expands the CEPC's capability to generate 4.3 million Higgs bosons, facilitating precise measurements of Higgs coupling at sub-percent levels, exceeding the precision expected from the HL-LHC by an order of magnitude. This Technical Design Report (TDR) follows the Preliminary Conceptual Design Report (Pre-CDR, 2015) and the Conceptual Design Report (CDR, 2018), comprehensively detailing the machine's layout and performance, physical design and analysis, technical systems design, R&D and prototyping efforts, and associated civil engineering aspects. Additionally, it includes a cost estimate and a preliminary construction timeline, establishing a framework for forthcoming engineering design phase and site selection procedures. Construction is anticipated to begin around 2027-2028, pending government approval, with an estimated duration of 8 years. The commencement of experiments could potentially initiate in the mid-2030s.Comment: 1106 page