A power efficient neural spike recording channel with data bandwidth reduction

This paper presents a mixed-signal neural spike recording channel which features, as an added value, a simple and low-power data compression mechanism. The channel uses a band-limited differential low noise amplifier and a binary search data converter, together with other digital and analog blocks for control, programming and spike characterization. The channel offers a self-calibration operation mode and it can be configured both for signal tracking (to raw digitize the acquired neural waveform) and feature extraction (to build a first-order PWL approximation of the spikes). The prototype has been fabricated in a standard CMOS 0.13μm and occupies 400μm×400μm. The overall power consumption of the channel during signal tracking is 2.8μW and increases to 3.0μW average when the feature extraction operation mode is programmed.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Integrated circuit implementation of fuzzy controllers

This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno’s method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 bits is achieved. The connection of these blocks according to a proposed architecture allows fuzzy chips with low silicon area whose inference speed is in the range of 2 Mega FLIPS (fuzzy logic inferences per second

A Review on ANFIS based Linearization of Non Linear Sensors

Low cost sensors having high sensitivity, better resolution and linear characteristics are required for industrial applications based on instrumentation and control. Unfortunately, the natural non linear characteristic of sensor itself and also the dynamic nature of the environment, aging effect, inherent sensor’s noise and data loss due to transients or intermittent faults affects the sensor characteristics non linearly. As the transfer characteristic of most sensors is nonlinear in nature, obtaining data from such a nonlinear sensor, by using an optimized device, has always been a design challenge. Linearization of nonlinear sensor characteristic in digital environment, is a vital step in the instrument signal conditioning process. This paper gives a brief review about how to overcome this nonlinear characteristic of the sensor using artificial intelligence such as  Hybrid Neuro Fuzzy Logic (HNFL) based on digital linearization technique using VLSI technology such as Field Programmable Gate Array (FPGA)

WITTEX: A Constellation of Three Small Satellite Radar Altimeters

WITTEX, named in honor of E. Witte, who in 1878 first discovered the geostrophic current equation, is an acronym for Water Inclination Topography and Technology Experiment. WITTEX consists of three co-planar small satellite radar altimeters launched on the same vehicle into a GEOSAT -class orbit. The proposed satellite constellation would support measurement for the first time of both orthogonal components of the ocean\u27s surface slope, rather than the single component seen by conventional instruments. The satellites are spaced by several kilometers along their orbit; Earth rotation causes their sub-satellite tracks to be laterally separated. Track separation can be readily adjusted by selection and autonomous control of inter-satellite spacing. If the satellite spacing were about 900 km, then the sub-satellite orbit tracks would fall approximately uniformly 53 km apart at the equator. This spacing is nearly optimal for observing oceanic eddy fields and surface energy transport. The enabling conceptual innovation is the delay-Doppler radar altimeter (DDA). Studies have shown that this technique yields more precise measurements than a conventional radar altimeter, yet it requires much less transmitted power. The notional instrument has two frequencies and an onboard water vapor radiometer, similar to TOPEX. The DDA approach, combined with recent advances in spacecraft technology, leads to substantial miniaturization; the goal is to use Pegasus as the launch vehicle. The enabling technologies include the Integrated Electronics Module (IEM), chip-on-board (COB), and the Command and Data Handling In-YourPalm (CDHIYP), all developed at The Johns Hopkins University Applied Physics Laboratory (JHU/APL). The WITTEX concept is a flexible, capable, unique, and cost-effective approach that will significantly advance the state of the art in both technical and scientific arenas

Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units

Tensor processing units (TPUs), specialized hardware accelerators for machine learning tasks, have shown significant performance improvements when executing convolutional layers in convolutional neural networks (CNNs). However, they struggle to maintain the same efficiency in fully connected (FC) layers, leading to suboptimal hardware utilization. In-memory analog computing (IMAC) architectures, on the other hand, have demonstrated notable speedup in executing FC layers. This paper introduces a novel, heterogeneous, mixed-signal, and mixed-precision architecture that integrates an IMAC unit with an edge TPU to enhance mobile CNN performance. To leverage the strengths of TPUs for convolutional layers and IMAC circuits for dense layers, we propose a unified learning algorithm that incorporates mixed-precision training techniques to mitigate potential accuracy drops when deploying models on the TPU-IMAC architecture. The simulations demonstrate that the TPU-IMAC configuration achieves up to $2.59\times$ performance improvements, and $88\%$ memory reductions compared to conventional TPU architectures for various CNN models while maintaining comparable accuracy. The TPU-IMAC architecture shows potential for various applications where energy efficiency and high performance are essential, such as edge computing and real-time processing in mobile devices. The unified training algorithm and the integration of IMAC and TPU architectures contribute to the potential impact of this research on the broader machine learning landscape

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC with signal-independent delta-I noise DfT scheme

This paper presents a 3.5GSps 6-bit current-steering DAC with auxiliary circuitry to assist testing in a 1V digital 28nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035mm2, making it suitable to embedding in VLSI systems, e.g. FPGA. To cope with the IC process variability, a unit element approach is generally employed. The 3 MSBs are implemented as 7 unary D/A cells and the 3 LSBs as 3 binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5kbits is placed on-chip, which is externally loaded in a serial way but internally read in an 8x time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output non-linearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC SFDR>40dB bandwidth is 0.8GHz, while the IM