A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3 ) over the temperature range from -22 C to 85 C. Fabricated in a baseline 65 nm CMOS technology, the frequency reference circuit occupies 0.11 mm

Integrated Electronics for Wireless Imaging Microsystems with CMUT Arrays

Integration of transducer arrays with interface electronics in the form of single-chip CMUT-on-CMOS has emerged into the field of medical ultrasound imaging and is transforming this field. It has already been used in several commercial products such as handheld full-body imagers and it is being implemented by commercial and academic groups for Intravascular Ultrasound and Intracardiac Echocardiography. However, large attenuation of ultrasonic waves transmitted through the skull has prevented ultrasound imaging of the brain. This research is a prime step toward implantable wireless microsystems that use ultrasound to image the brain by bypassing the skull. These microsystems offer autonomous scanning (beam steering and focusing) of the brain and transferring data out of the brain for further processing and image reconstruction. The objective of the presented research is to develop building blocks of an integrated electronics architecture for CMUT based wireless ultrasound imaging systems while providing a fundamental study on interfacing CMUT arrays with their associated integrated electronics in terms of electrical power transfer and acoustic reflection which would potentially lead to more efficient and high-performance systems. A fully wireless architecture for ultrasound imaging is demonstrated for the first time. An on-chip programmable transmit (TX) beamformer enables phased array focusing and steering of ultrasound waves in the transmit mode while its on-chip bandpass noise shaping digitizer followed by an ultra-wideband (UWB) uplink transmitter minimizes the effect of path loss on the transmitted image data out of the brain. A single-chip application-specific integrated circuit (ASIC) is de- signed to realize the wireless architecture and interface with array elements, each of which includes a transceiver (TRX) front-end with a high-voltage (HV) pulser, a high-voltage T/R switch, and a low-noise amplifier (LNA). Novel design techniques are implemented in the system to enhance the performance of its building blocks. Apart from imaging capability, the implantable wireless microsystems can include a pressure sensing readout to measure intracranial pressure. To do so, a power-efficient readout for pressure sensing is presented. It uses pseudo-pseudo differential readout topology to cut down the static power consumption of the sensor for further power savings in wireless microsystems. In addition, the effect of matching and electrical termination on CMUT array elements is explored leading to new interface structures to improve bandwidth and sensitivity of CMUT arrays in different operation regions. Comprehensive analysis, modeling, and simulation methodologies are presented for further investigation.Ph.D

Curvature of BEOL cantilevers in CMOS-MEMS processes

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents the curvature characterization results of released back-end-of-line 5 µm-wide cantilevers for two different 0.18-µm 1P6M complementary metal-oxide semiconductor microelectromechanical systems processes. Results from different runs and lots from each foundry are presented. The methodology and accuracy of the characterization approach, based on optical measurements of test cantilever curvature, are also discussed. Special emphasis is given to the curvature average and variability as a function of the number of stacked layers. Analythical equations for modeling the bending behavior of stacked cantilevers as a function of the tungsten (W) vias that join the metal layers are presented. In addition, the effect of various post-processing conditions and design techniques on the curvature of both single and stacked cantilevers is analyzed. In particular, surpassing certain time-dependent temperature stress conditions after release lead to curvature shifts larger than one order of magnitude. Also, the W via design was found to strongly affect the curvature of the test cantilevers.Peer ReviewedPostprint (author's final draft

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 μ m CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 μ W. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD)

A comprehensive high-level model for CMOS-MEMS resonators

2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a behavioral modeling technique for CMOS microelectromechanical systems (MEMS) microresonators that enables simulation of an MEMS resonator model in Analog Hardware Description Language format within a system-level circuit simulation. A 100-kHz CMOS-MEMS resonant pressure sensor has been modeled into Verilog-A code and successfully simulated within Cadence framework. Analysis has shown that simulation results of the reported model are in agreement with the device characterization results. As an application of the proposed methodology, simulation and results of the model together with an integrated monolithic low-noise amplifier is exemplified for detecting the position change of the resonator.Peer ReviewedPostprint (author's final draft

Non-Silicon MOSFETs and Circuits with Atomic Layer Deposited Higher-k Dielectrics

The quest for technologies beyond 14nm node complementary metal-oxide-semiconductor (CMOS) devices has now called for research on higher-k gate dielectrics integration with high mobility channel materials such as III-V semiconductors and germanium. Ternary oxides, such as La2-xYxO3 and LaAlO3, have been considered as strong candidates due to their high dielectric constants and good thermal stability. Meanwhile, the unique abilities of delivering large area uniform thin film, excellent controlling of composition and thickness to an atomic level, which are keys to ultra-scaled devices, have made atomic layer deposition (ALD) technique an excellent choice. In this thesis, we systematically study the atomic layer epitaxy (ALE) process realized by ALD, ALE higher-k dielectric integration, GaAs nMOSFETs and pMOSFETs on (111)A substrates, and their related CMOS digital logic gate circuits as well as ring oscillators. A record high drain current of 376 mA/mm and a small SS of 74 mV/dec are obtained from planar GaAs nMOSFETs with 1μm gate length. La2-xYxO3/GaAs(111)A interfaces are systematically investigated in both material and electrical aspects. The work has expanded the near 50 years GaAs MOSFETs research to an unprecedented level. Following the GaAs work, Ge n- and p-MOSFETs with epitaxial interfaces are also fabricated and studied. Beyond the conventional semiconductors, the complex oxide channel material SrTiO3 is also explored. Well-behaved LaAlO3/SrTiO3 nMOSFETs with a conducting channel at insulating ALD amorphous LaAlO3 - insulating crystalline SrTiO3 interface are also demonstrated