Lower bounds for dilation, wirelength, and edge congestion of embedding graphs into hypercubes

Interconnection networks provide an effective mechanism for exchanging data between processors in a parallel computing system. One of the most efficient interconnection networks is the hypercube due to its structural regularity, potential for parallel computation of various algorithms, and the high degree of fault tolerance. Thus it becomes the first choice of topological structure of parallel processing and computing systems. In this paper, lower bounds for the dilation, wirelength, and edge congestion of an embedding of a graph into a hypercube are proved. Two of these bounds are expressed in terms of the bisection width. Applying these results, the dilation and wirelength of embedding of certain complete multipartite graphs, folded hypercubes, wheels, and specific Cartesian products are computed

Outerplanar crossing numbers, the circular arrangement problem and isoperimetric functions

We extend the lower bound in [15] for the outerplanar crossing number (in other terminologies also called convex, circular and one-page book crossing number) to a more general setting. In this setting we can show a better lower bound for the outerplanar crossing number of hypercubes than the best lower bound for the planar crossing number. We exhibit further sequences of graphs, whose outerplanar crossing number exceeds by a factor of log n the planar crossing number of the graph. We study the circular arrangement problem, as a lower bound for the linear arrangement problem, in a general fashion. We obtain new lower bounds for the circular arrangement problem. All the results depend on establishing good isoperimetric functions for certain classes of graphs. For several graph families new near-tight isoperimetric functions are established

Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

Discrete Macaulay-Steiner Geometry

This thesis is concerned with discrete isoperimetric inequalities and Hilbert functions. Two generalizations of the Ahlswede-Cai local global principle are presented. These results give positive answers to two questions posed by Harper. One of these results is achieved by proving uniqueness of the lexicographic and colexicographic orders in two dimensions. The other result generalizes the technique which is commonly known as compression and includes almost all previously published results in this direction. The Ahlswede-Cai local global principle is a direct corollary of this result. Optimal downsets are studied in rectangles and triangles. All optimal downsets are found. The main result in this direction gives a unified description, optimal downsets are those that are a symmetrization/stabilization of initial segments of the lexicographic and colexicographic orders. Lindsay’s Theorem and the Ahlswede-Katona Edge Isoperimetric Theorem are corollaries. The theory of Macaulay posets is connected to that of Hilbert functions. Several old and new results in both commutative algebra and extremal combinatorics are obtained. Hoefel’s questions on applying Macaulay poset theory to commutative algebra is answered in the affirmative as a by product. A question of Bezrukov and Leck on taking the product of a Macaulay poset with a chain is answered by using a result of Mermin and Peeva. Several answers are given to a problem of Mermin and Peeva

Parallel Processing for VLSI CAD Applications a Tutorial

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research CorporationAuthor's name appears in front matter as Prithviraj Banerje

The connection machine

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.Bibliography: leaves 134-157.by William Daniel Hillis.Ph.D