17,304 research outputs found
Design, processing and testing of LSI arrays, hybrid microelectronics task
Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated
Contamination Control in Hybrid Microelectronic Modules. Part 1: Identification of Critical Process and Contaminants
Various hybrid processing steps, handling procedures, and materials are examined in an attempt to identify sources of contamination and to propose methods for the control of these contaminants. It is found that package sealing, assembly, and rework are especially susceptible to contamination. Moisture and loose particles are identified as the worst contaminants. The points at which contaminants are most likely to enter the hybrid package are also identified, and both general and specific methods for their detection and control are developed. In general, the most effective controls for contaminants are: clean working areas, visual inspection at each step of the process, and effective cleaning at critical process steps. Specific methods suggested include the detection of loose particles by a precap visual inspection, by preseal and post-seal electrical testing, and by a particle impact noise test. Moisture is best controlled by sealing all packages in a clean, dry, inert atmosphere after a thorough bake-out of all parts
NASA guidelines on report literature
NASA seeks for inclusion in its Scientific and Technical Information System research reports, conference proceedings, meeting papers, monographs, and doctoral and post graduate theses which relate to the NASA mission and objectives. Topics of interest to NASA are presented
Beam lead technology
Beam lead technology for microcircuit interconnections with applications to metallization, passivation, and bondin
Developing the knowledge-based human resources that support the implementation of the National Dual Training System (NDTS): evaluation of TVET teacher's competency at MARA Training Institutions
Development in the world of technical and vocational education and training (TVET)
on an ongoing basis is a challenge to the profession of the TVET-teachers to
maintain their performance. The ability of teachers to identify the competencies
required by their profession is very critical to enable them to make improvements in
teaching and learning. For a broader perspective the competency needs of the labour
market have to be matched by those developed within the vocational learning
processes. Consequently, this study has focused on developing and validating the
new empirical based TVET-teacher competency profile and evaluating teacher’s
competency. This study combines both quantitative and qualitative research
methodology that was designed to answer all the research questions. The new
empirical based competency profile development and TVET-teacher evaluation was
based upon an instructional design model. In addition, a modified Delphi technique
has also been adopted throughout the process. Initially, 98 elements of competencies
were listed by expert panel and rated by TVET institutions as important. Then,
analysis using manual and statistical procedure found that 112 elements of
competencies have emerged from seventeen (17) clusters of competencies. Prior to
that, using the preliminary TVET-teacher competency profile, the level of TVETteacher
competencies was found to be Proficient and the finding of 112 elements of
competencies with 17 clusters was finally used to develop the new empirical based
competency profile for MARA TVET-teacher. Mean score analysis of teacher
competencies found that there were gaps in teacher competencies between MARA
institutions (IKM) and other TVET institutions, where MARA-teacher was
significantly better than other TVET teacher. ANOVA and t-test analysis showed
that there were significant differences between teacher competencies among all
TVET institutions in Malaysia. On the other hand, the study showed that teacher’s
age, grade and year of experience are not significant predictors for TVET-teacher
competency. In the context of mastering the competency, the study also found that
three competencies are classified as most difficult or challenging, twelve
competencies are classified as should be improved, and eight competencies are
classified as needed to be trained. Lastly, to make NDTS implementation a reality
for MARA the new empirical based competency profile and the framework for
career development and training pathway were established. This Framework would
serve as a significant tool to develop the knowledge based human resources needed.
This will ensure that TVET-teachers at MARA are trained to be knowledgeable,
competent, and professional and become a pedagogical leader on an ongoing basis
towards a world class TVET-education system
VLSI Revisited - Revival in Japan
This paper describes the abundance of semiconductor consortia that have come into existence in Japan since the mid-1990s. They clearly reflect the ambition of the government - through its reorganized ministry METI and company initiatives - to regain some of the industrial and technological leadership that Japan has lost. The consortia landscape is very different in Japan compared with EU and the US. Outside Japan the universities play a much bigger and very important role. In Europe there has emerged close collaboration, among national government agencies, companies and the EU Commission in supporting the IT sector with considerable attention to semiconductor technologies. Another major difference, and possibly the most important one, is the fact that US and EU consortia include and mix partners from different areas of the semiconductor landscape including wafer makers, material suppliers, equipment producers and integrated device makers.semiconductors, Hitachi, Sony, Toshiba, Elpida, Renesas, Sematech, VLSI, JESSI, MEDEA, ASPLA, MIRAI, innovation system
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