Thermal Characterization and Lifetime Prediction of LED Boards for SSL Lamp

This work presents a detailed 3-D thermo-mechanical modelling of two LED board technologies to compare their performance. LED board are considered to be used in high power 800 lumen retrofit SSL (Solid State Lighting) lamp. Thermal, mechanical and life time properties are evaluated by numerical modelling. Experimental results measured on fabricated LED board samples are compared to calculated data. Main role of LED board in SSL lamp is to transport heat from LED die to a heat sink and keep the thermal stresses in all layers as low as possible. The work focuses on improving of new LED board thermal management. Moreover, reliability and lifetime of LED board has been inspected by numerical calculation and validated by experiment. Thermally induced stress has been studied for wide temperature range that can affect the LED boards (-40 to +125°C). Numerical modelling of thermal performance, thermal stress distribution and lifetime has been carried out with ANSYS structural analysis where temperature dependent stress-strain material properties have been taken into account. The objective of this study is to improve not only the thermal performance of new LED board, but also identification of potential problems from mechanical fatigue point of view. Accelerated lifetime testing (e.g., mechanical) is carried out in order to study the failure behaviour of current and newly developed LED board

A novel method for fatigue testing of MEMS devices containing movable elements

In this paper we present an electronic circuit for position or capacitance estimation of MEMS electrostatic actuators based on a switched capacitor technique. The circuit uses a capacitive divider configuration composed by a fixed capacitor and the variable capacitance of the electrostatic actuator for generating a signal that is a function of the input voltage and capacitive ratio. The proposed circuit can be used to actuate and to sense position of an electrostatic MEMS actuator without extra sensing elements. This approach is compatible with the requirements of most analog feedback systems and the circuit topology of pulsed digital oscillators (PDO).Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/EDA-Publishing

Thick-Film and LTCC Passive Components for High-Temperature Electronics

At this very moment an increasing interest in the field of high-temperature electronics is observed. This is a result of development in the area of wide-band semiconductors’ engineering but this also generates needs for passives with appropriate characteristics. This paper presents fabrication as well as electrical and stability properties of passive components (resistors, capacitors, inductors) made in thick-film or Low-Temperature Co-fired Ceramics (LTCC) technologies fulfilling demands of high-temperature electronics. Passives with standard dimensions usually are prepared by screen-printing whereas combination of standard screen-printing with photolithography or laser shaping are recommenced for fabrication of micropassives. Attainment of proper characteristics versus temperature as well as satisfactory long-term high-temperature stability of micropassives is more difficult than for structures with typical dimensions for thick-film and LTCC technologies because of increase of interfacial processes’ importance. However it is shown that proper selection of thick-film inks together with proper deposition method permit to prepare thick-film micropassives (microresistors, air-cored microinductors and interdigital microcapacitors) suitable for the temperature range between 150°C and 400°C

Optimizing construction of scheduled data flow graph for on-line testability

The objective of this work is to develop a new methodology for behavioural synthesis using a flow of synthesis, better suited to the scheduling of independent calculations and non-concurrent online testing. The traditional behavioural synthesis process can be defined as the compilation of an algorithmic specification into an architecture composed of a data path and a controller. This stream of synthesis generally involves scheduling, resource allocation, generation of the data path and controller synthesis. Experiments showed that optimization started at the high level synthesis improves the performance of the result, yet the current tools do not offer synthesis optimizations that from the RTL level. This justifies the development of an optimization methodology which takes effect from the behavioural specification and accompanying the synthesis process in its various stages. In this paper we propose the use of algebraic properties (commutativity, associativity and distributivity) to transform readable mathematical formulas of algorithmic specifications into mathematical formulas evaluated efficiently. This will effectively reduce the execution time of scheduling calculations and increase the possibilities of testability

A review of stencil printing for microelectronic packaging

PurposeThe purpose of this paper is to present a detailed overview of the current stencil printing process for microelectronic packaging.Design/methodology/approachThis paper gives a thorough review of stencil printing for electronic packaging including the current state of the art.FindingsThis article explains the different stencil technologies and printing materials. It then examines the various factors that determine the outcome of a successful printing process, including printing parameters, materials, apparatus and squeegees. Relevant technical innovations in the art of stencil printing for microelectronics packaging are examined as each part of the printing process is explained.Originality/valueStencil printing is currently the cheapest and highest throughput technique to create the mechanical and electrically conductive connections between substrates, bare die, packaged chips and discrete components. As a result, this process is used extensively in the electronic packaging industry and therefore such a review paper should be of interest to a large selection of the electronics interconnect and assembly community.</jats:sec

Thermal And Mechanical Analysis of High-power Light-emitting Diodes with Ceramic Packages

In this paper we present the thermal and mechanical analysis of high-power light-emitting diodes (LEDs) with ceramic packages. Transient thermal measurements and thermo-mechanical simulation were performed to study the thermal and mechanical characteristics of ceramic packages. Thermal resistance from the junction to the ambient was decreased from 76.1 oC/W to 45.3 oC/W by replacing plastic mould to ceramic mould for LED packages. Higher level of thermo-mechanical stresses in the chip were found for LEDs with ceramic packages despite of less mismatching coefficients of thermal expansion comparing with plastic packages. The results suggest that the thermal performance of LEDs can be improved by using ceramic packages, but the mounting process of the high power LEDs with ceramic packages is critically important and should be in charge of delaminating interface layers in the packages.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

Design, processing and testing of LSI arrays, hybrid microelectronics task

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated

Contamination Control in Hybrid Microelectronic Modules. Part 1: Identification of Critical Process and Contaminants

Various hybrid processing steps, handling procedures, and materials are examined in an attempt to identify sources of contamination and to propose methods for the control of these contaminants. It is found that package sealing, assembly, and rework are especially susceptible to contamination. Moisture and loose particles are identified as the worst contaminants. The points at which contaminants are most likely to enter the hybrid package are also identified, and both general and specific methods for their detection and control are developed. In general, the most effective controls for contaminants are: clean working areas, visual inspection at each step of the process, and effective cleaning at critical process steps. Specific methods suggested include the detection of loose particles by a precap visual inspection, by preseal and post-seal electrical testing, and by a particle impact noise test. Moisture is best controlled by sealing all packages in a clean, dry, inert atmosphere after a thorough bake-out of all parts

Low cost patterning of thin film

A novel route for the low-cost patterning of electrical thin films has been established. The process has been developed principally for the manufacture of thermocouples using high-speed reel-to-reel industrial techniques, but could be applied to the manufacture of a wide range of electronic devices including radio frequency identification (RFID) antennae, electrical interconnect, and passive electronic components. The procedure exploits high-volume processes directly to print self-removing masking layers. The process offers substantial advantages over traditional thin-film patterning methods including faster, cheaper production runs. Raw material use and wastage are greatly reduced, affording environmental benefits