Wavelength dependent light tunable resistive switching graphene oxide nonvolatile memory devices

This paper reports on the first optically tunable graphene oxide memristor device. Modulation of resistive switching memory by light opens the route to new optoelectronic devices that can be switched optically and read electronically. Applications include integrated circuits with memory elements switchable by light and optically reconfigurable and tunable synaptic circuits for neuromorphic computing and brain-inspired, artificial intelligence systems. In this report, planar and vertical structured optical resistive switching memristors based on graphene oxide are reported. The device is switchable by either optical or electronic means, or by a combination of both. In addition the devices exhibit a unique wavelength dependence that produces reversible and irreversible properties depending on whether the irradiation is long or short wavelength light, respectively. For long wavelength light, the reversible photoconductance effect permits short-term dynamic modulation of the resistive switching properties of the light, which has application as short-term memory in neuromorphic computing. In contrast, short wavelength light induces both the reversible photoconductance effect and an irreversible change in the memristance due to reduction of the graphene oxide. This has important application in the fabrication of cloned neural networks with factory defined weights, enabling the fast replication of artificial intelligent chips with pre-trained information

Chua mem-components for adaptive RF metamaterials

Chua's mem-components are ideal for creating adaptive metasurfaces for manipulating EM waves given that they hold their state without external biases. In this paper, we propose a generic adaptive reactive element that is in fact a memcapacitor/meminductor. This element makes use of a polymer that demonstrates reversible trans-cis photochemical isomerization, thus making it possible to change the distance between two conductive plates by up to 25%. Furthermore, a design methodology for utilizing these devices is presented

Capacitive effects and memristive switching in three terminal multilayered MoS<inf>2</inf>devices

We report on the electrical properties of gated two-terminal multilayered molybdenum disulfide (MoS2) memristor devices having a planar architecture. The approach based on highly dispersed MoS2 flakes drop cast onto a bottom gated Si/SiO2 (100nm) wafer containing metal Pd contact electrodes yields devices that exhibit a number of complex properties including memristive and capacitive effects as well as multiple non-zero-crossing current-voltage hysteresis effects. The devices also show a reaction to a varying gate bias. An increasingly positive gate led to the devices displaying a linear ohmic I-V response while an increasingly negative gate bias drove the system to behave more memristive with a widening hysteresis loop

MR4RF: MEM-device with impedance and their usage with impedance matching networks for passive RFID tags in the UHF

The passive RFID tag in the UHF has been employed in several different applications including, tracking, logistics, and as a sensing platform for the Internet of things (IoT). The tag is ideal for this industry due to its unique design. It harvests all of its energy from the environment, and is small, cheap, and requires little to no maintenance. However, there are two major issues limiting the potential of the passive RFID systems: the limited power harvested by the tag, and the high susceptibility to interference and coupling. In particular, dynamic environments render the traditionally fixed, RF impedance matching network ineffective. A novel design for a flexible Impedance-Switching Network (ISN) for passive RFID tags in the UHF is presented in this thesis. This novel approach can maximize power harvested by the tag. We propose two approaches to implementing the ISN. First, a more traditional design with a series of varactors is developed and studied. Each varactor is placed in parallel impedance lanes that are controlled via a feedback loop to maximize harvested power. A four-lane ISN is designed, tested, and tuned. The simulations and experiments demonstrate that ISN is capable of compensating for negative effect of mutual coupling in a ferromagnetic-reach environment. The second design employs a new material called a memristive switch that can replace the varactors in the ISN. State of a memristive switch is non-volatile and requires little energy to operate, thus making it ideal for passive RFID tags. We are the first to characterize the Co3O4 based memristive switch in UHF range. The results show that it can be employed as a varying capacitor in the RF front-end design. We propose three general configurations for the ISNs --Abstract, page iii

A walk on the frontier of energy electronics with power ultra-wide bandgap oxides and ultra-thin neuromorphic 2D materials

Altres ajuts: the ICN2 is funded also by the CERCA programme / Generalitat de CatalunyaUltra-wide bandgap (UWBG) semiconductors and ultra-thin two-dimensional materials (2D) are at the very frontier of the electronics for energy management or energy electronics. A new generation of UWBG semiconductors will open new territories for higher power rated power electronics and deeper ultraviolet optoelectronics. Gallium oxide - GaO(4.5-4.9 eV), has recently emerged as a suitable platform for extending the limits which are set by conventional (-3 eV) WBG e.g. SiC and GaN and transparent conductive oxides (TCO) e.g. In2O3, ZnO, SnO2. Besides, GaO, the first efficient oxide semiconductor for energy electronics, is opening the door to many more semiconductor oxides (indeed, the largest family of UWBGs) to be investigated. Among these new power electronic materials, ZnGa2O4 (-5 eV) enables bipolar energy electronics, based on a spinel chemistry, for the first time. In the lower power rating end, power consumption also is also a main issue for modern computers and supercomputers. With the predicted end of the Moores law, the memory wall and the heat wall, new electronics materials and new computing paradigms are required to balance the big data (information) and energy requirements, just as the human brain does. Atomically thin 2D-materials, and the rich associated material systems (e.g. graphene (metal), MoS2 (semiconductor) and h-BN (insulator)), have also attracted a lot of attention recently for beyond-silicon neuromorphic computing with record ultra-low power consumption. Thus, energy nanoelectronics based on UWBG and 2D materials are simultaneously extending the current frontiers of electronics and addressing the issue of electricity consumption, a central theme in the actions against climate chang

Agenda: Second International Workshop on Thin Films for Electronics, Electro-Optics, Energy and Sensors (TFE3S)

University of Dayton’s Center of Excellence for Thin Film Research and Surface Engineering (CETRASE) is delighted to organize its second international workshop at the University of Dayton’s Research Institute (UDRI) campus in Dayton, Ohio, USA. The purpose of the new workshop is to exchange technical knowledge and boost technical and educational collaboration activities within the thin film research community through our CETRASE and the UDRI

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Integration of Ferroelectric HfO2 onto a III-V Nanowire Platform

The discovery of ferroelectricity in CMOS-compatible oxides, such as doped hafnium oxide, has opened new possibilities for electronics by reviving the use of ferroelectric implementations on modern technology platforms. This thesis presents the ground-up integration of ferroelectric HfO2 on a thermally sensitive III-V nanowire platform leading to the successful implementation of ferroelectric transistors (FeFETs), tunnel junctions (FTJs), and varactors for mm-wave applications. As ferroelectric HfO2 on III-V semiconductors is a nascent technology, a special emphasis is put on the fundamental integration issues and the various engineering challenges facing the technology.The fabrication of metal-oxide-semiconductor (MOS) capacitors is treated as well as the measurement methods developed to investigate the interfacial quality to the narrow bandgap III-V materials using both electrical and operando synchrotron light source techniques. After optimizing both the films and the top electrode, the gate stack is integrated onto vertical InAs nanowires on Si in order to successfully implement FeFETs. Their performance and reliability can be explained from the deeper physical understanding obtained from the capacitor structures.By introducing an InAs/(In)GaAsSb/GaSb heterostructure in the nanowire, a ferroelectric tunnel field effect transistor (ferro-TFET) is fabricated. Based on the ultra-short effective channel created by the band-to-band tunneling process, the localized potential variations induced by single ultra-scaled ferroelectric domains and individual defects are sensed and investigated. By intentionally introducing a gate-source overlap in the ferro-TFET, a non-volatile reconfigurable single-transistor solution for modulating an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing is implemented.Finally, by fabricating scaled ferroelectric MOS capacitors in the front-end with a dedicated and adopted RF and mm-wave backend-of-line (BEOL) implementation, the ferroelectric behavior is captured at RF and mm-wave frequencies

ANALOG SIGNAL PROCESSING SOLUTIONS AND DESIGN OF MEMRISTOR-CMOS ANALOG CO-PROCESSOR FOR ACCELERATION OF HIGH-PERFORMANCE COMPUTING APPLICATIONS

Emerging applications in the field of machine vision, deep learning and scientific simulation require high computational speed and are run on platforms that are size, weight and power constrained. With the transistor scaling coming to an end, existing digital hardware architectures will not be able to meet these ever-increasing demands. Analog computation with its rich set of primitives and inherent parallel architecture can be faster, more efficient and compact for some of these applications. The major contribution of this work is to show that analog processing can be a viable solution to this problem. This is demonstrated in the three parts of the dissertation. In the first part of the dissertation, we demonstrate that analog processing can be used to solve the problem of stereo correspondence. Novel modifications to the algorithms are proposed which improves the computational speed and makes them efficiently implementable in analog hardware. The analog domain implementation provides further speedup in computation and has lower power consumption than a digital implementation. In the second part of the dissertation, a prototype of an analog processor was developed using commercially available off-the-shelf components. The focus was on providing experimental results that demonstrate functionality and to show that the performance of the prototype for low-level and mid-level image processing tasks is equivalent to a digital implementation. To demonstrate improvement in speed and power consumption, an integrated circuit design of the analog processor was proposed, and it was shown that such an analog processor would be faster than state-of-the-art digital and other analog processors. In the third part of the dissertation, a memristor-CMOS analog co-processor that can perform floating point vector matrix multiplication (VMM) is proposed. VMM computation underlies some of the major applications. To demonstrate the working of the analog co-processor at a system level, a new tool called PSpice Systems Option is used. It is shown that the analog co-processor has a superior performance when compared to the projected performances of digital and analog processors. Using the new tool, various application simulations for image processing and solution to partial differential equations are performed on the co-processor model

Nanoionic Resistive‐Switching Devices

Advances in the understanding of nanoscale ionic processes in solid‐state thin films have led to the rapid development of devices based on coupled ionic–electronic effects. For example, ion‐driven resistive‐switching (RS) devices have been extensively studied for future memory applications due to their excellent performance in terms of switching speed, endurance, retention, and scalability. Recent studies further suggest that RS devices are more than just resistors with tunable resistance; instead, they exhibit rich and complex internal ionic dynamics that equip them with native information‐processing capabilities, particularly in the temporal domain. RS effects induced by the migration of different types of ions, often driven by an electric field, are discussed. It is shown that, by taking advantage of the different state variables controlled by the ionic processes, important synaptic functions can be faithfully implemented in solid‐state devices and networks. Recent efforts on improving the controllability of ionic processes to optimize device performance are also discussed, along with new opportunities for material design and engineering enabled by the ability to control ionic processes at the atomic scale.Solid‐state resistive‐switching devices driven by nanoscale ionic processes are reviewed, with the focus on the rich ionic dynamics that enable natural implementation of a range of biological synaptic and neuron functions. Efforts to control ion redistribution at the atomic scale have led to improved device performance, and enabled applications based on reconfigurable nanostructures and materials through controlled ionic processes in solid‐state devices.Peer Reviewedhttps://deepblue.lib.umich.edu/bitstream/2027.42/151267/1/aelm201900184_am.pdfhttps://deepblue.lib.umich.edu/bitstream/2027.42/151267/2/aelm201900184.pd