A fully digital power supply noise thermometer

Power Supply Noise (PSN) is one of the main concerns in scaled technology circuits, both if performance reliability must be assured and if power supply is to be dynamically reduced for dissipation regulation. In this paper we propose a new system for digitally sensing Power Supply and Ground levels that can be both transferred to the output for verification purposes and used by a control block within the circuit under test (CUT) for the activation of power aware policies. The sensor system shows very low overhead in terms of power and area, and works at the nominal CUT frequency. It allows to change on-site the Power Supply and Ground ranges to be sensed and, after a fine tuning, can be arranged for a process variation aware measures. This sensor is fully digital and standard cell based and can be used for every type of architecture on a systematic basis for PSN measure as scan chains are for fault verification. It thus represents a change of paradigm in the way in which PSN measure systems are thought nowaday

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Design and construction of a Cherenkov imager for charge measurement of nuclear cosmic rays

A proximity focusing Cherenkov imager called CHERCAM, has been built for the charge measurement of nuclear cosmic rays with the CREAM instrument. It consists of a silica aerogel radiator plane across from a detector plane equipped with 1,600 1" diameter photomultipliers. The two planes are separated by a ring expansion gap. The Cherenkov light yield is proportional to the charge squared of the incident particle. The expected relative light collection accuracy is in the few percents range. It leads to an expected single element separation over the range of nuclear charge Z of main interest 1 < Z < 26. CHERCAM is designed to fly with the CREAM balloon experiment. The design of the instrument and the implemented technical solutions allowing its safe operation in high altitude conditions (radiations, low pressure, cold) are presented.Comment: 24 pages, 19 figure

Cancellation of crosstalk-induced jitter

A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre- or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10^sup-12 BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps

Performance characterisation of a new photo-microsensor based sensing head for displacement measurement

This paper presents a robust displacement sensor with nanometre-scale resolution over a micrometre range. It is composed of low cost commercially available slotted photo-microsensors (SPMs). The displacement sensor is designed with a particular arrangement of a compact array of SPMs with specially designed shutter assembly and signal processing to significantly reduce sensitivity to ambient light, input voltage variation, circuit electronics drift, etc. The sensor principle and the characterisation results are described in this paper. The proposed prototype sensor has a linear measurement range of 20 μm and resolution of 21 nm. This kind of sensor has several potential applications, including mechanical structural deformation monitoring system