O-Band Subwavelength Grating Filters in a Monolithic Photonics Technology

The data communications industry has begun transitioning from electrical to optical interconnects in datacenters in order to overcome performance bottlenecks and meet consumer needs. To mitigate the costs associated with this change and achieve performance for 5G and beyond, it is crucial to explore advanced photonic devices that can enable high-bandwidth interconnects via wavelength-division multiplexing (WDM) in photonic integrated circuits. Subwavelength grating (SWG) filters have shown great promise for WDM applications. However, the small feature sizes necessary to implement these structures have prohibited them from penetrating into industrial applications. To explore the manufacturability and performance of SWG filters in an industrial setting, we fabricate and characterize O-band subwavelength grating filters using the monolithic photonics technology at GLOBALFOUNDRIES (GF). We demonstrate a low drop channel loss of -1.2 dB with a flat-top response, a high extinction ratio of -30 dB, a 3 dB channel width of 5 nm and single-source thermal tunability without shape distortion. This filter structure was designed using elements from the product design kit provided by GF and functions in a compact footprint of 0.002 mm2 with a minimum feature size of 150 nm.Comment: 4 pages, 3 figure

Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

On Regularity and Integrated DFM Metrics

Transistor geometries are well into the nanometer regime, keeping with Moore's Law. With this scaling in geometry, problems not significant in the larger geometries have come to the fore. These problems, collectively termed variability, stem from second-order effects due to the small geometries themselves and engineering limitations in creating the small geometries. The engineering obstacles have a few solutions which are yet to be widely adopted due to cost limitations in deploying them. Addressing and mitigating variability due to second-order effects comes largely under the purview of device engineers and to a smaller extent, design practices. Passive layout measures that ease these manufacturing limitations by regularizing the different layout pitches have been explored in the past. However, the question of the best design practice to combat systematic variations is still open. In this work we explore considerations for the regular layout of the exclusive-OR gate, the half-adder and full-adder cells implemented with varying degrees of regularity. Tradeoffs like complete interconnect unidirectionality, and the inevitable introduction of vias are qualitatively analyzed and some factors affecting the analysis are presented. Finally, results from the Calibre Critical Feature Analysis (CFA) of the cells are used to evaluate the qualitative analysis

Voltage controlled oscillators for 40Gbit/s cascaded bit-interleaving PON

Technologies such as the Internet-of-Things and cloud services demand dynamic bandwidth allocation flexibility, which is not offered by the currently deployed solutions. The Bit-Interleaving PON (BiPON) and its cascaded extension the Cascaded Bit-Interleaving PON (CBI-PON) offer a solution that allows to increase bandwidths, reduce power consumption and have a much more flexible dynamic bandwidth allocation scheme. CBI-PON consists of multiple levels of BiPON with different line rates. For each of these line rates, clock-and-data recovery must be performed, which requires a set of different Voltage Controlled Oscillators (VCOs). This paper presents the VCOs designed for the CABINET chip, an implementation of a CBI-PON network device, allowing clock-and-data recovery for 40Gbit/s, 10 Gbit/s and 2.5 Gbit/s line rates

FOCSI: A new layout regularity metric

Technical ReportDigital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce these ICs systematic subwavelength lithography failures. However, there is no metric to evaluate and compare the layout regularity of those regular designs. In this paper we propose a new layout regularity metric called Fixed Origin Corner Square Inspection (FOCSI). FOCSI allows the comparison and quantification of designs in terms of regularity and for any given degree of granularity. When FOCSI is oriented to the evaluation of regularity while applying Lithography Enhancement Techniques, it comprehends layout layers measurements considering the optical interaction length and combines them to obtain the complete layout regularity measure. Examples are provided for 32-bit adders in the 90 nm technology node for the Standard Cell approach and for Via-Configurable Transistor Array regular designs. We show how layouts can be sorted accurately even if their degree of regularity is similar.Preprin

Mid-IR heterogeneous silicon photonics

In this paper we discuss silicon-based photonic integrated circuit technology for applications beyond the telecommunication wavelength range. Silicon-on-insulator and germanium-on-silicon passive waveguide circuits are described, as well as the integration of III-V semiconductors, IV-VI colloidal nanoparticle films and GeSn alloys on these circuits for increasing the functionality. The strong nonlinearity of silicon combined with the low nonlinear absorption in the mid-infrared is exploited to generate picosecond pulse based supercontinuum sources and optical parametric oscillators that can be used as spectroscopic sensor sources