Stochastic multiple-stream decoding of Cortex codes

International audienceCortex codes are short length block codes having a large Hamming distance. Their modular construction, based on simple and very short block codes, yield to difficulties in efficiently decoding them with digital decoders implementing the Sum-Product algorithm. However, this construction lends itself to analog decoding with performance close to ML decoding as was recently demonstrated. A digital decoding method close to analog decoding is stochastic decoding. This paper brings the two together to design a Cortex stochastic architecture with good decoding performance. Moreover, the proposed stochastic decoder architecture is simplified when compared to the customary one. Instead of edge or tracking forecast memories the proposed architecture uses multiple streams to represent the same probability and deterministic shufflers. This results in a more efficient architecture in terms of ratio between data throughput and hardware complexity. Finally, the proposed method offers decoding performance similar to a Min-Sum decoder with 50 iterations

Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed.Comment: 16 pages, 22 figures, 2 table

Fault Tolerance of Stochastic Decoders for Error Correcting Codes

Low-density Parity-check (LDPC) codes are very powerful linear error-correcting codes, first introduced by Gallager in 1963. They are now used in many communication standards due to their ability to achieve near Shannon-capacity performance. Stochastic decoding is a hardware-efficient method of iterative decoding of LDPC codes. In this work, we investigate the capability of stochastic decoding to tolerate circuit soft errors while maintaining good bit error rate performance and low error floor. Soft errors can be intended faults as a result of either supply voltage scaling to reduce power consumption or overclocking the system to achieve a higher throughput. They can also be unintended faults as a result of temperature or process variations. We develop two models to emulate these circuit errors at the system level. We apply our models to two standardized LDPC codes (10GBASE-T and WiMAX). Simulation results show that stochastic decoding is very tolerant to faults and errors, where it can tolerate a probability of setup time violation of 0.1 in the wires of the decoder. Hence, stochastic decoding can be very useful in systems with very low power or high performance requirements where we can push the limits of power or speed by lowering the supply voltage or highly overclocking the system while maintaining good performance. In addition, a chip has been designed and sent to fabrication to do post-silicon validation and verify our models

A Novel Stochastic Decoding of LDPC Codes with Quantitative Guarantees

Low-density parity-check codes, a class of capacity-approaching linear codes, are particularly recognized for their efficient decoding scheme. The decoding scheme, known as the sum-product, is an iterative algorithm consisting of passing messages between variable and check nodes of the factor graph. The sum-product algorithm is fully parallelizable, owing to the fact that all messages can be update concurrently. However, since it requires extensive number of highly interconnected wires, the fully-parallel implementation of the sum-product on chips is exceedingly challenging. Stochastic decoding algorithms, which exchange binary messages, are of great interest for mitigating this challenge and have been the focus of extensive research over the past decade. They significantly reduce the required wiring and computational complexity of the message-passing algorithm. Even though stochastic decoders have been shown extremely effective in practice, the theoretical aspect and understanding of such algorithms remains limited at large. Our main objective in this paper is to address this issue. We first propose a novel algorithm referred to as the Markov based stochastic decoding. Then, we provide concrete quantitative guarantees on its performance for tree-structured as well as general factor graphs. More specifically, we provide upper-bounds on the first and second moments of the error, illustrating that the proposed algorithm is an asymptotically consistent estimate of the sum-product algorithm. We also validate our theoretical predictions with experimental results, showing we achieve comparable performance to other practical stochastic decoders.Comment: This paper has been submitted to IEEE Transactions on Information Theory on May 24th 201

Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders

[EN] Stochastic low-density parity-check decoders (SLDPCs) have found favor recently both for correcting transmission errors as well as for improving the hardware efficiency. The main drawback of these decoders is that they require hundreds of time periods to decode each frame, but their chip area is smaller than that of their fixed-point counterparts, so they can achieve higher hardware efficiency and may consume less energy. In this paper, we propose a novel extrinsic information transfer chart technique for characterizing the iterative decoding convergence of all the sequences involved in the SLDPC. We have conceived a new model, which takes into consideration not only the sequences exchanged between the decoders but also the sequences generated inside the variable-node decoder (those which are stored in the edge memories). In this way, the model is able to predict the number of decoding iterations required for achieving iterative decoding convergence, as confirmed by own decoder simulations. The proposed technique offers new insights into the operation of SLDPCs, which will facilitate improved designs for the research community.Professor L. Hanzo would like to give thanks to the ERC for the financial support of this Advanced Fellow Grant.Pérez Pascual, MA.; Hamilton, A.; Maunder, RG.; Hanzo, L. (2018). Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders. IEEE Access. 6:55741-55753. https://doi.org/10.1109/ACCESS.2018.2872113S5574155753

Improving the tolerance of stochastic LDPC decoders to overclocking-induced timing errors: a tutorial and design example

Channel codes such as Low-Density Parity-Check (LDPC) codes may be employed in wireless communication schemes for correcting transmission errors. This tolerance to channel-induced transmission errors allows the communication schemes to achieve higher transmission throughputs, at the cost of requiring additional processing for performing LDPC decoding. However, this LDPC decoding operation is associated with a potentially inadequate processing throughput, which may constrain the attainable transmission throughput. In order to increase the processing throughput, the clock period may be reduced, albeit this is at the cost of potentially introducing timing errors. Previous research efforts have considered a paucity of solutions for mitigating the occurrence of timing errors in channel decoders, by employing additional circuitry for detecting and correcting these overclocking-induced timing errors. Against this background, in this paper we demonstrate that stochastic LDPC decoders (LDPC-SDs) are capable of exploiting their inherent error correction capability for correcting not only transmission errors, but also timing errors, even without the requirement for additional circuitry. Motivated by this, we provide the first comprehensive tutorial on LDPC-SDs. We also propose a novel design flow for timing-error-tolerant LDPC decoders. We use this to develop a timing error model for LDPC-SDs and investigate how their overall error correction performance is affected by overclocking. Drawing upon our findings, we propose a modified LDPC-SD, having an improved timing error tolerance. In a particular practical scenario, this modification eliminates the approximately 1 dB performance degradation that is suffered by an overclocked LDPC-SD without our modification, enabling the processing throughput to be increased by up to 69.4%, which is achieved without compromising the error correction capability or processing energy consumption of the LDPC-SD