Pattern classification for layout hotspots

The final objective of an integrated circuit design is to produce a layout, that is, a geometrical representation of the circuit where the geometrical shapes correspond to patters that will be formed by layers of metal, oxide, and semiconductors. These patterns are essentially descriptions that will be used to print the circuit through chemical, thermal and photographic processes. To ensure the layout can be used to print the circuit with no defects, it is necessary to run design rules check. This verification searches for patterns that violate design rules, which makes it impossible to guarantee defect-free printing. However, some layout patterns may present printability problems even when design rules are respected. To solve this problem, physical verification flows are applied to the layout with the objective of detecting and treating such patterns. The sheer number of these layout printability hotspots and the fact that they are sometimes similar to each other suggests that the physical verification flow can be sped up by clustering together similar patterns. In this work, we address the problem of complex shape partitioning, incorporating an algorithm with complexity O(n5=2) into the layout hotspot clustering flow, which allows for clustering of hotspots in benchmarks with complex polygons. Furthermore, a study of the viability of a machine learning flow for incremental clustering is conducted, covering the choice of features and analysis of candidate models.O objetivo final do fluxo de projeto de um circuito é produzir um leiaute, uma representação geométrica do circuito, onde as formas geométricas correspondem aos padrões que serão formados por camadas de metal, óxido e semicondutores. Esses padrões são essencialmente descrições que serão usadas para imprimir o circuito através de processos químicos, térmicos e fotográficos. Para garantir que o leiaute possa ser usado para impressão de um circuito integrado sem defeitos, é necessário executar verificações de regras de projeto. Essa verificação encontra padrões que violam regras que inviabilizariam a garantia de impressão sem defeitos. Porém, alguns padrões do leiaute podem apresentar problemas na impressão mesmo quando a checagem das regras de projeto não encontra erros. Para solucionar esse problema, fluxos de verificação física são aplicados no leiaute com o objetivo de detectar e tratar tais padrões. A grande quantidade de regiões com problemas de impressão e a similaridade entre elas sugere que o fluxo de verificação física pode ser acelerado ao se agrupar padrões similares. Neste trabalho, o problema de particionamento de polígonos complexos é abordado, e um algoritmo de particionamento de complexidade O(n5=2) é incorporado ao fluxo de classificação e agrupamento de regiões de interesse, permitindo que casos de teste com polígonos complexos tenham suas regiões de interesse agrupadas. Além disso, um estudo sobre a viabilidade de um fluxo de aprendizado de máquina é conduzido, cobrindo a escolha de atributos e a análise de diferentes modelos candidatos

Integrating openstreetmap data and sentinel-2 Imagery for classifying and monitoring informal settlements

Dissertation submitted in partial fulfilment of the requirements for the degree of Master of Science in Geospatial TechnologiesThe identification and monitoring of informal settlements in urban areas is an important step in developing and implementing pro-poor urban policies. Understanding when, where and who lives inside informal settlements is critical to efforts to improve their resilience. This study aims at integrating OSM data and sentinel-2 imagery for classifying and monitoring the growth of informal settlements methods to map informal areas in Kampala (Uganda) and Dar es Salaam (Tanzania) and to monitor their growth in Kampala. Three building feature characteristics of size, shape and Distance to nearest Neighbour were derived and used to cluster and classify informal areas using Hotspot Cluster analysis and ML approach on OSM buildings data. The resultant informal regions in Kampala were used with Sentinel-2 image tiles to investigate the spatiotemporal changes in informal areas using Convolutional Neural Networks (CNNs). Results from Optimized Hot Spot Analysis and Random Forest Classification show that Informal regions can be mapped based on building outline characteristics. An accuracy of 90.3% was achieved when an optimally trained CNN was executed on a test set of 2019 satellite image tiles. Predictions of informality from new datasets for the years 2016 and 2017 provided promising results on combining different open source geospatial datasets to identify, classify and monitor informal settlements

CHIP: Clustering hotspots in layout using integer programming

Clustering algorithms have been explored in recent years to solve hotspot clustering problem in Integrated Circuit design. With various applications in Design for Manufacturability flow such as hotspot library generation, systematic yield optimization and design space exploration, generating good quality clusters along with their representative clips is of utmost importance. With several generic clustering algorithms at our disposal, hotspots can be clustered based on the distance metric defined while satisfying some tolerance conditions. However, the clusters generated from generic clustering algorithms need not achieve optimal results. In this paper, we introduce two optimal integer linear programming formulations based on triangle inequality to solve the problem of minimizing cluster count while satisfying given constraints. Apart from minimizing cluster count, we generate representative clips that best represent the clusters formed. We achieve better cluster count for both formulations in most test cases as compared to the results published in literature on the ICCAD 2016 contest benchmarks as well as the reference results reported in the ICCAD 2016 contest websit

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots