Spread spectrum techniques for indoor wireless IR communications

Multipath dispersion and fluorescent light interference are two major problems in indoor wireless infrared communications systems. Multipath dispersion introduces intersymhol interference at data rates above 10 Mb/s, while fluorescent light induces severe narrowband interference to baseband modulation schemes commonly used such as OOK and PPM. This article reviews the research into the application of direct sequence spread spectrum techniques to ameliorate these key channel impairments without having to resort to complex signal processing techniques. The inherent properties of a spreading sequence are exploited in order to combat the ISI and narrowband interference. In addition, to reduce the impact of these impairments, the DSSS modulation schemes have strived to be bandwidth-efficient and simple to implement. Three main DSSS waveform techniques have been developed and investigated. These are sequence inverse keying, complementary sequence inverse keying, and M-ary biorthogonal keying (MBOK). The operations of the three systems are explained; their performances were evaluated through simulations and experiments for a number of system parameters, including spreading sequence type and length. By comparison with OOK, our results show that SIK, CSIK, and MBOK are effective against multipath dispersion and fluorescent light interference becausc the penalties incurred on the DSSS schemes are between 0-7 dB, while the penalty on OOK in the same environment is more than 17 dB. The DSSS solution for IR wireless transmission demonstrates that a transmission waveform can he designed to remove the key channel impairments in a wireless IR system

Simulated Assessment of Interference Effects in Direct Sequence SpreadSpectrum (DSSS) QPSK Receiver

This research developed and validated a generic simulation for a direct sequence spread spectrum (DSSS), using differential phase shift keying (DPSK) and phase shift keying (PSK) modulations, providing the flexibility for assessing intentional interference effect using DSSS quadrature phase shift keying receiver (QPSK) with matched filtering as a reference. The evaluation compares a comprehensive pool of jamming waveforms at pass-band that include continuous wave (CW) interference, broad-band jamming, partial-band interference and pulsed interference. The methodology for jamming assessment included comparing the bit error rate (BER) versus required jamming to signal ratio (JSR) for different interferers using the Monte Carlo approach. This thesis also analyzes the effect of varying the jammer bandwidth for broad-band jammers including broad-band noise (BBN), frequency hopping interference (FHI), comb- spectrum interference (CSI), multi-tone jamming (MTJ), random frequency modulated interference (RFMI) and linear frequency modulated interference (LFMI). Also, the effect of changing the duty cycle for pulsed CW waveforms is compared with the worst case pulsed jamming equation. After the evaluation of different interferers, the research concludes that pulsed binary phase shift keying (BPSK) jamming is the most effective technique, whereas the CW tone jamming and CW BPSK interference result are least effective. It is also concluded that by finding an optimum bandwidth, FHI and BBN improves the required JSR by approximately 2.1 dB, RFMI and LFMI interference by 0.9 and 1.5 dB respectively. Alternately, MTJ and CSI improves their effectiveness in 4.1 dB and 3.6 dB respectively, matching the performance of the pulsed BPSK jammer

Wavelet Domain Communication System (WDCS): Design, Model, Simulation, and Analysis

A proposed wavelet domain communication system (WDCS) using transform domain processing is demonstrated as having enhanced interference avoidance capability under adverse environmental conditions. The WDCS system samples the environment and uses the wavelet transform, to determine interference presence and time/scale location. A digital communication waveform (basis function) is subsequently designed in the wavelet domain to specifically avoid regions containing interference. The WDCS basis function is data modulated prior to transmission. Assuming perfect synchronization, the receiver replicates a locally generated basis function for correlating with the received signal and demodulating the data. The proposed system is modeled and simulation results are obtained using MATLAB. Bit error rate is the metric for analysis and performance comparisons. Relative to an equivalent DSSS, the WDCS provided bit error performance improvement in several different interference scenarios. The system also demonstrated comparable performance to a developmental TDCS while providing significant improvement in scenarios containing swept-tone interference. The system was evaluated using a signal bit energy-to- noise power level (E(beta)/N(omega) of 4.0 dB and interference energy-to-signal energy (I/E) ratios ranging from 0 dB to 16.0 dB. As defined, performance improvement metrics representing the ratio of DSSS-to-WDCS and DSSS-to-TDCS bit error rates were used for characterizing performance. For antipodal data modulation, the average (over all interference scenarios) DSSS-to-WDCS performance improvement was 12.4 dB, approximately equal to the DSSS-to-TDCS (comparable performance). For binary orthogonal data modulation, the average DSSS-to-WDCS improvement was 5.7 dB vs. 6.8 dB for the DSSS-to-TDCS comparison. These results indicate the proposed WDCS is a viable option for interference avoidance communications and worthy of further study

Ultra Wide Band Multiple Access Performance Using TH-PPM and DS-BPSK Modulations

The increasing demand for portable, high data rate communications has focused much attention on wireless technology. Ultra Wide Band (UWB) waveforms have the ability to deliver megabits of information while maintaining low average power consumption. In accordance with recent FCC ruling, UWB systems are now allowed to operate in the unlicensed spectrum of 3.1 to 10.6 GHz, motivating renewed interest in the forty year old concept of impulse radio. Gaussian monocycles produce UWB waveforms occupying large bandwidths with multiple access (MA) capability enabled by spread spectrum techniques. Time Hopping (TH) and Direct Sequence (DS) modulations are considered here for UWB MA applications. This work extends Gold coding results and characterizes UWB performance using Simulated Annealing (SA) and Random Integer (RI) codes for TH and DS UWB applications. TH-PPM and DS-BPSK performance is evaluated using simulated probability of bit error P(sub b) under MA interference (MAI), multipath interference (MPI), and narrow band interference (NBI) conditions for synchronous and asynchronous networks

Performance Study of Hybrid Spread Spectrum Techniques

This thesis focuses on the performance analysis of hybrid direct sequence/slow frequency hopping (DS/SFH) and hybrid direct sequence/fast frequency hopping (DS/FFH) systems under multi-user interference and Rayleigh fading. First, we analyze the performance of direct sequence spread spectrum (DSSS), slow frequency hopping (SFH) and fast frequency hopping (FFH) systems for varying processing gains under interference environment assuming equal bandwidth constraint with Binary Phase Shift Keying (BPSK) modulation and synchronous system. After thorough literature survey, we show that hybrid DS/FFH systems outperform both SFH and hybrid DS/SFH systems under Rayleigh fading and multi-user interference. Also, both hybrid DS/SFH and hybrid DS/FFH show performance improvement with increasing spreading factor and decreasing number of hopping frequencies

Design of software radio

Software Define Radio (SDR) has become a prevalent technology in wireless systems. In SDR some or all of the signal specific handling is implemented in software functions, while other functions like decimation, interpolation, digital up-conversion and digital down conversion are done on reprogrammable Digital Signal Processor or Field Programmable Gate Arrays.Twelve laboratory exercises have been designed to lead the student through the process of using the Universal Software Radio peripheral (USRP) hardware and GNU Radio open source software

Design of software radio

Software Define Radio (SDR) has become a prevalent technology in wireless systems. In SDR some or all of the signal specific handling is implemented in software functions, while other functions like decimation, interpolation, digital up-conversion and digital down conversion are done on reprogrammable Digital Signal Processor or Field Programmable Gate Arrays.Twelve laboratory exercises have been designed to lead the student through the process of using the Universal Software Radio peripheral (USRP) hardware and GNU Radio open source software

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation