Low power low noise analog front-end IC design for biomedical sensor interface

Ph.DDOCTOR OF PHILOSOPH

A Multi-Channel Low-Power System-on-Chip for in vivo NeuralSpike Recording

This paper reports a multi-channel neural spike recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 64-channel low-power low-noise analog front-end, a single 8-bit analog-todigital converter (ADC), followed by digital signal compression and transmission units. The 400-MHz transmitter employs a Manchester-Coded Frequency Shift Keying (MC-FSK) modulator with low modulation index. In this way a 1.25-Mbit/s data rate is delivered within a band of about 3 MHz. Compression of the raw data is implemented by detecting the action potentials (APs) and storing 20 samples for each spike waveform. The choice greatly improves data quality and allows single neuron identification. A larger than 10-m transmission range is reached with an overall power consumption of 17.2 mW. This figure translates into a power budget of 269 μW per channel, which is in line with the results in literature but allowing a larger transmission distance and more efficient wireless link bandwidth occupation. The implemented IC was mounted on a small and light printed circuit board to be used during neuroscience experiments with freely-behaving rats. Powered by 2 AAA batteries the system can work continuously for more than 100 hours allowing long-lasting neural spike recordings

Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

LOW- VOLTAGE HIGH EFFICIENCY ANALOG-TO-DIGITAL CONVERTER FOR BIOMEDICAL SENSOR INTERFACE

Ph.DDOCTOR OF PHILOSOPH

Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.

Understanding dynamics of the brain has tremendously improved due to the progress in neural recording techniques over the past five decades. The number of simultaneously recorded channels has actually doubled every 7 years, which implies that a recording system with a few thousand channels should be available in the next two decades. Nonetheless, a leap in the number of simultaneous channels has remained an unmet need due to many limitations, especially in the front-end recording integrated circuits (IC). This research has focused on increasing the number of simultaneously recorded channels and providing modular design approaches to improve the integration and expansion of 3-D recording microsystems. Three analog front-ends (AFE) have been developed using extremely low-power and small-area circuit techniques on both the circuit and system levels. The three prototypes have investigated some critical circuit challenges in power, area, interface, and modularity. The first AFE (16-channels) has optimized energy efficiency using techniques such as moderate inversion, minimized asynchronous interface for data acquisition, power-scalable sampling operation, and a wide configuration range of gain and bandwidth. Circuits in this part were designed in a 0.25μm CMOS process using a 0.9-V single supply and feature a power consumption of 4μW/channel and an energy-area efficiency of 7.51x10^15 in units of J^-1Vrms^-1mm^-2. The second AFE (128-channels) provides the next level of scaling using dc-coupled analog compression techniques to reject the electrode offset and reduce the implementation area further. Signal processing techniques were also explored to transfer some computational power outside the brain. Circuits in this part were designed in a 180nm CMOS process using a 0.5-V single supply and feature a power consumption of 2.5μW/channel, and energy-area efficiency of 30.2x10^15 J^-1Vrms^-1mm^-2. The last AFE (128-channels) shows another leap in neural recording using monolithic integration of recording circuits on the shanks of neural probes. Monolithic integration may be the most effective approach to allow simultaneous recording of more than 1,024 channels. The probe and circuits in this part were designed in a 150 nm SOI CMOS process using a 0.5-V single supply and feature a power consumption of only 1.4μW/channel and energy-area efficiency of 36.4x10^15 J^-1Vrms^-1mm^-2.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98070/1/ashmouny_1.pd

RD53 Wafer Testing for the ATLAS ITk Pixel Detector

RD53 is the research and development group at CERN, responsible for developing and producing the next generation of readout chips for the ATLAS and CMS pixel detector upgrades at the HL-LHC. Its most recent development ITkPix is the first full-scale 65 nm hybrid pixel-detector. ITkPix consists of more than one billion transistors with a high triplication ratio in order to cope with the high particle and therefore radiation density at the heart of ATLAS. The chips will be located as close as possible to the interaction point to optimize impact parameter resolution. The ITkPix chip features a 5Gbit connection, with special data compression to deal with high hit intensities. In addition to that, a low power, low noise analog front-end is used, to ensure high readout speeds and low detection thresholds. A failure of chips at the heart of ATLAS is problematic. Therefore, thorough testing before and duringtheproduction phase is necessary. For thispurpose, Bonn has developed bdaq, a fast and versatile simulation, testing and analysis environment, making small-and large-scale testing for ITkPix and its successors possible. This talk will give an overview over the testing environment, while focusing on large scale wafer testing results to evaluatetheITkPix fitness for its deployment at the HL-LHC

RD53B Wafer Testing for the ATLAS ITk Pixel Detector

RD53 is the research and development group at CERN responsible for developing and producing the next generation of readout chips for the ATLAS and CMS pixel detectors at the HL-LHC. Its most recent development ITkPix/RD53B is the rst full-scale 65 nm hybrid pixel-readout chip. ITkPix consists of more than one billion transistors with high memory triplication ratio in order to cope with the high particle density at the heart of ATLAS. The chips will be located as close as possible to the interaction point to optimize impact parameter resolution. The ITkPix chip features a 5Gbit connection, with special data compression to deal with high hit intensities. In addition to that, a low power, low noise analog front-end is used, to ensure high readout speeds and low detection thresholds. A failure of chips at the heart of ATLAS is problematic. Therefore, thorough testing before and during production is necessary. For this purpose, Bonn has developed BDAQ53, a fast and versatile simulation and testing environment, allowing for small-and large-scale testing for ITkPix and its successor chips. This conference note will give an overview over the testing environment, while focusing on large-scale wafer testing to evaluate ITkPix's tness for its deployment at the HL-LHC