Novel CCII-based Field Programmable Analog Array and its Application to a Sixth-Order Butterworth LPF

In this paper, a field programmable analog array (FPAA) is proposed. The proposed FPAA consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice such that the CABs are directly connected to each other. This structure improves the overall frequency response of the chip by decreasing the parasitic capacitances in the signal path. The CABS of the FPAA is based on a novel fully differential digitally programmable current conveyor (DPCCII). The programmability of the DPCCII is achieved using digitally controlled three-bit MOS ladder current division network. No extra biasing circuit is required to generate specific analog control voltage signals. The DPCCII has constant standby power consumption, offset voltage, bandwidth and harmonic distortions over all its programming range. A sixth-order Butterworth tunable LPF suitable for WLAN/WiMAX receivers is realized on the proposed FPAA. The filter power consumption is 5.4mW from 1V supply; it’s cutoff frequency is tuned from 5.2 MHz to 16.9 MHz. All the circuits are realized using 90nm CMOS technology from TSMC. All simulations are carried out using Cadence

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Fully integrated millimeter-wave CMOS phased arrays

A decade ago, RF CMOS, even at low gigahertz frequencies, was considered an oxymoron by all but the most ambitious and optimistic. Today, it is a dominating force in most commercial wireless applications (e.g., cellular, WLAN, GPS, BlueTooth, etc.) and has proliferated into areas such as watt level power amplifiers (PA) [1] that have been the undisputed realm of compound semiconductors. This seemingly ubiquitous embracement of silicon and particularly CMOS is no accident. It stems from the reliable nature of silicon process technologies that make it possible to integrated hundreds of millions of transistors on a single chip without a single device failure, as evident in today’s microprocessors. Applied to microwave and millimeter wave applications, silicon opens the door for a plethora of new topologies, architectures, and applications. This rapid adoption of silicon is further facilitated by one’s ability to integrate a great deal of in situ digital signal processing and calibration [2]. Integration of high-frequency phased-array systems in silicon (e.g., CMOS) promises a future of low-cost radar and gigabit-per-second wireless communication networks. In communication applications, phased array provides an improved signal-to-noise ratio via formation of a beam and reduced interference generation for other users. The practically unlimited number of active and passive devices available on a silicon chip and their extremely tight control and excellent repeatability enable new architectures (e.g., [3]) that are not practical in compound semiconductor module-based approaches. The feasibility of such approaches can be seen through the discussion of an integrated 24GHz 4-element phased-array transmitter in 0.18μm CMOS [2], capable of beam forming and rapid beam steering for radar applications. On-chip power amplifiers (PA), with integrated 50Ω output matching, make this a fully-integrated transmitter. This CMOS transmitter and the 8-element phased-array SiGe receiver in [5], demonstrate the feasibility of 24GHz phased-array systems in silicon-based processes

A Fully Differential CMOS Potentiostat

A CMOS potentiostat for chemical sensing in a noisy environment is presented. The potentiostat measures bidirectional electrochemical redox currents proportional to the concentration of a chemical down to pico-ampere range. The fully differential architecture with differential recording electrodes suppresses the common mode interference. A 200μm×200μm prototype was fabricated in a standard 0.35μm standard CMOS technology and yields a 70dB dynamic range. The in-channel analog-to-digital converter (ADC) performs 16-bit current-tofrequency quantization. The integrated potentiostat functionality is validated in electrical and electrochemical experiments

A CMOS 100 MHz continuous-time seventh order 0.05° equiripple linear phase leapfrog multiple loop feedback Gm-C filter

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A novel 100 MHz CMOS Gm-C seventh-order 0.05° equiripple linear phase low-pass multiple loop feedback (MLF) filter based on leapfrog (LF) topology is presented. The filter is implemented using a fully-differential linear, high performance operational transconductance amplifier (OTA) based on cross-coupled pairs. PSpice simulations in a standard TSMC 0.25 μm CMOS process and with a single 5 V power supply have shown that the cut-off frequency of the filter without and with gain boost ranges from 8-32 MHz and 15-100 MHz, respectively. With gain boost, total harmonic distortion (THD) for a differential input voltage Vid of 315 mVpp at 1 MHz is less than -40 dB, dynamic range at 1% THD is over 55 dB, output noise with bandwidth 500 MHz is only 300 μVRMS, and power consumption is 322 mW

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5° and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB

Design of an integrated analog controller for a Class-D Audio Amplifier

An integrated analog controller for a self-oscillating class-D audio power amplifier is designed in a 0.35 μm CMOS technology for a 3.3 Volt power supply. It is intended to be used with an external output stage and passive filter, for medium power applications of upto a few 100 Watts. The controller was optimized with regard to its loop gain to suppress the distortion of the output stage. In typical commercially available output stages, the distortion is dominated by dead time effects and the THD can be as low as 20 dB. The controller uses self-oscillation to generate the carrier. To control the self-oscillation a second order phase shift network is embedded in the loop. To increase the loop gain a fifth-order loop filter is added. For a switching frequency of 400kHz the controller achieves a loop gain of 51 dB, nearly flat over the audio band. For reasons of flexibility, the order of the controller is made programmable, as well as the dead time and the delay in the loop. Full spice simulations of the controller combined with an external 120 Watt output stage indicate that a THD of upto 80 dB (better than 0.01%) can be obtained even under the worst case condition of a dead time of 50 ns

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area

Inverter-Based Low-Voltage CCII- Design and Its Filter Application

This paper presents a negative type second-generation current conveyor (CCII-). It is based on an inverter-based low-voltage error amplifier, and a negative current mirror. The CCII- could be operated in a very low supply voltage such as ±0.5V. The proposed CCII- has wide input voltage range (±0.24V), wide output voltage (±0.24V) and wide output current range (±24mA). The proposed CCII- has no on-chip capacitors, so it can be designed with standard CMOS digital processes. Moreover, the architecture of the proposed circuit without cascoded MOSFET transistors is easily designed and suitable for low-voltage operation. The proposed CCII- has been fabricated in TSMC 0.18μm CMOS processes and it occupies 1189.91 x 1178.43μm2 (include PADs). It can also be validated by low voltage CCII filters

High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology