Programmable photonics : an opportunity for an accessible large-volume PIC ecosystem

We look at the opportunities presented by the new concepts of generic programmable photonic integrated circuits (PIC) to deploy photonics on a larger scale. Programmable PICs consist of waveguide meshes of tunable couplers and phase shifters that can be reconfigured in software to define diverse functions and arbitrary connectivity between the input and output ports. Off-the-shelf programmable PICs can dramatically shorten the development time and deployment costs of new photonic products, as they bypass the design-fabrication cycle of a custom PIC. These chips, which actually consist of an entire technology stack of photonics, electronics packaging and software, can potentially be manufactured cheaper and in larger volumes than application-specific PICs. We look into the technology requirements of these generic programmable PICs and discuss the economy of scale. Finally, we make a qualitative analysis of the possible application spaces where generic programmable PICs can play an enabling role, especially to companies who do not have an in-depth background in PIC technology

CMOL: Second Life for Silicon?

This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reconfigurable Boolean-logic circuits, and mixed-signal neuromorphic networks. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with the extremely high potential density of molecular-scale two-terminal nanodevices. Relatively large critical dimensions of CMOS components and the "bottom-up" approach to nanodevice fabrication may keep CMOL fabrication costs at affordable level. At the same time, the density of active devices in CMOL circuits may be as high as 1012 cm2 and that they may provide an unparalleled information processing performance, up to 1020 operations per cm2 per second, at manageable power consumption.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

A Millimeter Wave MIMO Testbed for 5G Communications

This paper presents a 2 x 2 millimeter wave (mm-wave) multiple-input-multiple-output (MIMO) testbed that operates at around 30 GHz. The link assessment of the system operating at 26.25 GHz was carried out on a test bench, with a short communication distance between the transmitting and receiving antennas. A user-programmable, reconfigurable and real-time signal processing field-programmable gate arrays (FPGAs)-based software defined radio (SDR) system was employed as part of the testbed to validate the system-level performance for a downlink time division long-term evolution (TD-LTE) duplex scheme. Constellation diagram for quadrature phase shift keying (QPSK) digital modulation were acquired while the testbed was operating at 30 GHz. The testbed could be employed for the development of signal test, communication algorithm and measurement metrology for 5G communications.Comment: 89th ARFTG Microwave Measurement Conference (ARFTG 2017

Mask Programmable CMOS Transistor Arrays for Wideband RF Integrated Circuits

A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4-22-GHz range are implemented. The amplifiers achieve high gain-bandwidth products (79-96 GHz) despite their standard multistage designs. These amplifiers are based on an identical transistor array interconnected with application specific coplanar waveguide (CPW) transmission lines and on-chip capacitors and resistors. CPW lines are implemented using a one-metal-layer post-processing technology over a thick Parylene-N (15 mum ) dielectric layer that enables very low loss lines (~0.6 dB/mm at 20 GHz) and high-performance CMOS amplifiers. The proposed integration approach has the potential for implementing cost-efficient and high-performance RF and microwave circuits with a short turnaround time

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

Column-row addressing of thermo-optic phase shifters for controlling large silicon photonic circuits

We demonstrate a time-multiplexed row-column addressing scheme to drive thermo-optic phase shifters in a silicon photonic circuit. By integrating a diode in series with the heater, we can connect $N \times M$ heaters in an matrix topology to $N$ row and $M$ column lines. The heaters are digitally driven with pulse-width modulation, and time-multiplexed over different channels. This makes it possible to drive the circuit without digital-to-analog converters, and using only $M+N$ wires. We demonstrate this concept with a $1 \times 16$ power splitter tree with 15 thermo-optic phase shifters that are controlled in a $3 \times 5$ matrix, connected through 8 bond pads. This technique is especially useful in silicon photonic circuits with many tuners but limited space for electrical connections