Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

Design and manufacturing of a Selective Laser Sintering test bench to test sintering materials

The goal of this project is to design and build a prototype of recoating system for a laser cutting machine to turn it into a selective laser sintering printing machine. This prototype will be used to study new sintering materials and to design, if decided, a SLS 3D printing Machine (Selective Laser Sintering). This project has been developed in the installations and funded by Fundació CIM. The project develops the mechanical design and the electronic system design. Both parts are explained on this paper, so new users can use the machine and can understand the system. With this paper, it is expected that it can be improved in a future to test other parameters and configurations. The paper is divided in three basic blocks that are summed up here: The first block is an introduction to the 3D printing technologies. The most used of them are explained and selective laser sintering is explained in deep. With this block the reader can understand why it is important to develop the SLS technology and what has to be done to improve the machines and the technology. The second block is a discussion on the mechanical design of the machine. The general idea of the machine is explained so the user can understand why the machine is designed in this way. After that, each part is detailed to see how the different mechanical challenges where overtaken. At the end of the block, there is a small calculations section needed on the electronic part. The third block is an extensive explanation of the electronic system that controls and moves the machine. In that block, the different components are explained so the user can understand its basics working principles. It is also explained how the selection of the electronic components was done. Then everything is put together to see the whole electronic system. Along with this paper, there are annexes that provide some extra information for the reader. One of this annexes refers to the mechanical part and the other one has some datasheets and coding for the electronic section. The whole design has been done in SOLIDWORKS cad software and its electric extension ELECWORKS. The programming job was done with Arduino compiler

Index to nasa tech briefs, issue number 2

Annotated bibliography on technological innovations in NASA space program

Conceptual design and feasibility evaluation model of a 10 to the 8th power bit oligatomic mass memory. Volume 1: Conceptual design

The oligatomic (mirror) thin film memory technology is a suitable candidate for general purpose spaceborne applications in the post-1975 time frame. Capacities of around 10 to the 8th power bits can be reliably implemented with systems designed around a 335 million bit module. The recommended mode was determined following an investigation of implementation sizes ranging from an 8,000,000 to 100,000,000 bits per module. Cost, power, weight, volume, reliability, maintainability and speed were investigated. The memory includes random access, NDRO, SEC-DED, nonvolatility, and dual interface characteristics. The applications most suitable for the technology are those involving a large capacity with high speed (no latency), nonvolatility, and random accessing

Automated Synthesis of SEU Tolerant Architectures from OO Descriptions

SEU faults are a well-known problem in aerospace environment but recently their relevance grew up also at ground level in commodity applications coupled, in this frame, with strong economic constraints in terms of costs reduction. On the other hand, latest hardware description languages and synthesis tools allow reducing the boundary between software and hardware domains making the high-level descriptions of hardware components very similar to software programs. Moving from these considerations, the present paper analyses the possibility of reusing Software Implemented Hardware Fault Tolerance (SIHFT) techniques, typically exploited in micro-processor based systems, to design SEU tolerant architectures. The main characteristics of SIHFT techniques have been examined as well as how they have to be modified to be compatible with the synthesis flow. A complete environment is provided to automate the design instrumentation using the proposed techniques, and to perform fault injection experiments both at behavioural and gate level. Preliminary results presented in this paper show the effectiveness of the approach in terms of reliability improvement and reduced design effort

Equipment concept design and development plans for microgravity science and applications research on space station: Combustion tunnel, laser diagnostic system, advanced modular furnace, integrated electronics laboratory

Taking advantage of the microgravity environment of space NASA has initiated the preliminary design of a permanently manned space station that will support technological advances in process science and stimulate the development of new and improved materials having applications across the commercial spectrum. Previous studies have been performed to define from the researcher's perspective, the requirements for laboratory equipment to accommodate microgravity experiments on the space station. Functional requirements for the identified experimental apparatus and support equipment were determined. From these hardware requirements, several items were selected for concept designs and subsequent formulation of development plans. This report documents the concept designs and development plans for two items of experiment apparatus - the Combustion Tunnel and the Advanced Modular Furnace, and two items of support equipment the Laser Diagnostic System and the Integrated Electronics Laboratory. For each concept design, key technology developments were identified that are required to enable or enhance the development of the respective hardware

Integrated Application of Active Controls (IAAC) technology to an advanced subsonic transport project: Current and advanced act control system definition study. Volume 2: Appendices

The current status of the Active Controls Technology (ACT) for the advanced subsonic transport project is investigated through analysis of the systems technical data. Control systems technologies under examination include computerized reliability analysis, pitch axis fly by wire actuator, flaperon actuation system design trade study, control law synthesis and analysis, flutter mode control and gust load alleviation analysis, and implementation of alternative ACT systems. Extensive analysis of the computer techniques involved in each system is included

Testing Embedded Memories in Telecommunication Systems

Extensive system testing is mandatory nowadays to achieve high product quality. Telecommunication systems are particularly sensitive to such a requirement; to maintain market competitiveness, manufacturers need to combine reduced costs, shorter life cycles, advanced technologies, and high quality. Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults. This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view. In particular, advanced BIST-based solutions are analyzed, and two significant industrial case studies presente