Design and Analysis of 8x8 Wallace Tree Multiplier using GDI and CMOS Technology

Multiplier is a small unit of an arithmetic circuit that is widely used in Digital filters, Digital Signal Processing, microprocessors and communication applications etc. In today's scenario compact and small digital devices are critical concern in the field of VLSI design, which should perform fast as well as low power consumption. Optimizing the delay, area and power of a multiplier is a major design issues, as area and speed are usually conflicting constraints. A Wallace tree multiplier is an improved version of tree base multiplier. The main aim of this paper is a reconfigurable 8x8 Wallace Tree multiplier using CMOS and GDI technology. This is efficient in power and regularity without increase in delay and area. The generation of partial products in parallel using AND gates. The addition of partial products is reducing using Wallace Tree which is divided into levels. Therefore there will be a certain reduction in the power consumption, since power is provided only to the level that is involved in computation and the remaining two levels remain off

LOW POWER MULTIPLIER USING ALGORITHMIC NOISE TOLERANT ARCHITECTURE

: A multiplier is one of the key hardware blocks in most digital signal processing (DSP) systems. Typical DSP applications where a multiplier plays an important role include digital filtering, digital communications and spectral analysis (Ayman.A et al (2001)). Many current DSP applications are targeted at portable, battery-operated systems, so that power dissipation becomes one of the primary design constraints. Since multipliers are rather complex circuits and must typically operate at a high system clock rate, reducing the delay of a multiplier is an essential part of satisfying the overall design. In this project a multiplier block has been designed through the algorithmic noise tolerance architectures (ANT) by using Wallace multiplier. A reliable low power multiplier design with the fixed width multiplier block through the reduced precision replica redundancy (RPR) and main block design with Wallace multiplier . The new architecture can meet the high accuracy, low power consumption and area efficiency when compared with previous multiplier circuit

Design a Low Power Built in Self-Test (BIST) Architecture for Fast Multiplier and Optimize in Terms of Real Time Functionality

Aiming low power during testing, Maypresent a methodology for derivingBIST Architecture forfast Multipliers. In my propose Researchseveral design rules for designing the Wallace tree in order to be fully testable under the cell fault model. The proposed low power BISTArchitecture for the derived multipliers is achieved by: (i) IntroducingTest Pattern Generators (ii) Properly assigning the TPGsoutputs to the multiplier inputs and(iii) Significantly reducing the test vector length. In this work, I have implemented 4bit * 4bit Multiplier with many test pattern generators (TPG) alternative. A BIST TPG Architecture was use of 6 bit counter. I have calculated operation speed, time delay, area, power consumption for Design. Reductionof power dissipationachieved byproperly assigning the TPG output to the multiplier input,significantly reducing the test set length, suitableTPG built of a6-bit counter DOI: 10.17762/ijritcc2321-8169.150317

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0µW/MHz versus 10.9µW/MHz and more for 0.25µm CMOS technology at 0.75V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V dd to ground resistance, hence decreasing leakage dissipation (0.55nW versus 0.84nW in CSM and 0.94nW in Wallace

Design and Implementation of Faster and Low Power Multipliers

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. Thus making them suitable for various high speed, low power, and compact VLSI implementations. However area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best trade off solution among the both of them. Generally as we know multiplication goes in two basic steps. Partial product and then addition. Hence in this paper we have first tried to design different adders and compare their speed and complexity of circuit i.e. the area occupied. And then we have designed Wallace tree multiplier then followed by Booth’s Wallace multiplier and have compared the speed and Power consumption in them. While comparing the adders we found out that Ripple Carry Adder had a smaller area while having lesser speed, in contrast to which Carry Select Adders are high speed but posses a larger area. And a Carry Look Ahead Adder is in between the spectrum having a proper trade off between time and area complexities. After designing and comparing the adders we turned to multipliers. Initially we went for Parallel Multiplier and then Wallace Tree Multiplier. In the mean time we learned that delay amount was considerably reduced when Carry Save Adders were used in Wallace Tree applications. Then we turned to Booths Multiplier and designed Radix-4 modified booth multiplier and analyzed the performance of all the multipliers. After that we turned to different methods of power optimization, of which we could only complete a few like we went for designing different recoding schemes and their corresponding partial product generator scheme. After that we designed these recoders and PP generators and found out the time delays and area covered and power consumed by each scheme. We took into consideration that since all the PP generators take a huge amount of area we need to go for simplest of the designs for them and also side by side we need to ensure that we don’t have much switching actions in the circuit. After this we even modified one of the recoding schemes to lower the delay and power required by the circuit. The result of our project helps us to make a proper choice of different multipliers in fabricating in different arithmetic units as well as making a choice among different adders in different digital applications according to requirements. All the programs and results have been given in the following sections. Further work on Low Power Techniques on different multipliers needs to be done in order to make us choose a proper multiplier in accordance with the requirements by making the best possible trade off choice between Speed and Power in different circumstances

Performance Analysis and Verification of Multipliers

Multiplication is a fundamental operation in most arithmetic computing systems. Multipliers have large area, long latency and consume considerable power. The number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. Then, to limit the power dissipation, alternative solutions at each level of abstraction are used. At the algorithm and architecture level, this paper addresses Low-Power, High Speed and Less Area multiplier design systematically from two aspects: internal efforts considering multiplier architectures and external efforts considering input data characteristics.  For internal efforts, we consider recoding optimization for partial product generation, operand representation optimization, and structure optimization of partial product reduction. For external efforts, we consider signal gating to deactivate portions of a full-precision multiplier.  Several multiplier types are studied:  array multipliers, wallace multipliers, booth multiplier. In accordance to that we specify that the comparison and verification of the multiplier on basics of time delay, power and area.

A comparative study of novel variable set multiplier scheme and other column compression multipliers

The extensive use of multipliers in high-performance processors has been driving the demand for low-power, high-speed multipliers. This report presents a novel fast multiplier scheme that performs reduction based on non-uniform grouping in the partial product matrix. In every stage, the partial products are grouped into sets of variable heights before reduction. The algorithm is presented and compared with Wallace, Dadda, and Reduced Area Multipliers in terms of gate complexity, delay, interconnects and power utilization for 4-bit, 7-bit, 8-bit and 12-bit versions. The proposed design is observed to have a gate count of 3% lower than Wallace multipliers, comparable to Dadda in most of the cases but slightly higher than Reduced Area multipliers. To fulfill the study, a 12-bit version of each multiplier was implemented in structural Verilog with basic gates and synthesized using Xilinx Vivado. The net cell usage statistics and the power utilization values were extracted and compared. It was observed that the proposed design has better power efficiency than the other multipliers for the examined cases.Electrical and Computer Engineerin