Students’ acceptance towards kahoot application in mastering culinary terminology

Kahoot! is a game-based learning platform used to review students’ knowledge, for formative assessment and provides an opportunity not only to assess students' conceptual understanding but also to build new knowledge through further clarification during or after the game. The objective of this study is to assess the acceptability of culinary students in the use of Kahoot! application for mastery the culinary terminology. This study aimed to identify students' acceptance of learning applications, to identify students' acceptance of Kahoot! use in terms of memory as well as students' level of mastering Kahoot! in the learning process. This study is a descriptive study that used a five-point Likert scale questionnaire as an instrument. A total of 48 second year students from the Catering program were used as the study sample. The collected data were analyzed using Statistical Package for Social Science Version 23.0 for Windows (SPSS). The results show that the aspect of students' level of mastering the culinary terminology using Kahoot! application is high with a mean score of 4.55. Whereas the students’ acceptance of Kahoot! as a learning application, was also high with a mean score of 4.44. Finally, the students’ acceptance of the culinary terminology tested using Kahoot! is high with a mean score of 4.45

CMOS optical-sensor array with high output current levels and automatic signal-range centring

A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range centring according to illumination conditions are presented. The high output current levels allow the use of these devices in continuoustime asynchronous imagers, as well as in high-sampling-frequency applications

Asynchronous Nano-Electronics: Preliminary Investigation

This paper is a preliminary investigation in implementing asynchronous QDI logic in molecular nano-electronics, taking into account the restricted geometry, the lack of control on transistor strengths, the high timing variations. We show that the main building blocks of QDI logic can be successfully implemented; we illustrate the approach with the layout of an adder stage. The proposed techniques to improve the reliability of QDI apply to nano-CMOS as well

Nonphotolithographic nanoscale memory density prospects

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations

A 100-MIPS GaAs asynchronous microprocessor

The authors describe how they ported an asynchronous microprocessor previously implemented in CMOS to gallium arsenide, using a technology-independent asynchronous design technique. They introduce new circuits including a sense-amplifier, a completion detection circuit, and a general circuit structure for operators specified by production rules. The authors used and tested these circuits in a variety of designs

Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

Subthreshold Dual Mode Logic

In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. This is achieved with a simple and intuitive design concept. SPICE and Monte Carlo simulations compare performance, power dissipation, and robustness of the proposed DML gates to their CMOS and domino counterparts in the 80-nm process. Measurements of an 80-nm test chip are presented in order to prove the proposed concept

VLSI design of the tiny RISC microprocessor

This report describes the Tiny RISC microprocessor designed at UC Irvine. Tiny RISC is a 16-bit microprocessor and has a RISC-style architecture. The chip was fabricated by MOSIS [1] in a 2μm n-well CMOS technology. The processor has a cycle time of 70 ns