The Decomposition of DSP’s Control Logic Block for Power Reduction

The paper considers the architecture and low power design aspects of the digital signal processing block embedded into a three-phase integrated power meter IC. Utilized power reduction techniques were focused on the optimization of control logic block. The operations that control unit performs are described together with power optimization results

State assignment for sequential circuits using multi-objective genetic algorithm

In this study, a new approach using a multi-objective genetic algorithm (MOGA) is proposed to determine the optimal state assignment with less area and power dissipations for completely and incompletely specified sequential circuits. The goal is to find the best assignments which reduce the component count and switching activity. The MOGA employs a Pareto ranking scheme and produces a set of state assignments, which are optimal in both objectives. The ESPRESSO tool is used to optimise the combinational parts of the sequential circuits. Experimental results are given using a personal computer with an Intel CPU of 2.4 GHz and 2 GB RAM. The algorithm is implemented using C++ and fully tested with benchmark examples. The experimental results show that saving in components and switching activity are achieved in most of the benchmarks tested compared with recent published research

Computer aided synthesis and optimisation of electronic logic circuits

In this thesis, a variety of algorithms for synthesis and optimisation of combinational and sequential logic circuits are developed. These algorithms could be part of new commercial EGAD package for future VLSI digital designs. The results show that considerable saving in components can be achieved resulting in simpler designs that are smaller, cheaper, consume less power and easier to test. The purpose of generating different sets of coefficients related to Reed Muller (RM) is that they contain different number of terms; therefore the minimum one can be selected to design the circuits with reduced gate count. To widen the search space and achieve better synthesis tools, representations of Mixed Polarity Reed Muller (MPRM), Mixed Polarity Dual Reed Muller (MPDRM), and Pseduo Kronecker Reed Muller (PKRO RM) expansions are investigated. Efficient and fast combinatorial techniques and algorithms are developed for the following: â Bidirectional conversion between MPRM/ MPDRM form and Fixed Polarity Reed Muller forms (FPRM)/Fixed Polarity Dual Reed Muller forms (FPDRM) form respectively. The main advantages for these techniques are their simplicity and suitability for single and multi output Boolean functions. â Computing the coefficients of any polarity related to PKRO_RM class starting from FPRM coefficients or Canonical Sum of Products (CSOP). â Computing the coefficients of any polarity related to MPRM/or MPDRM directly from standard form of CSOP/Canonical Product of sums (CPOS) Boolean functions, respectively. The proposed algorithms are efficient in terms of CPU time and can be used for large functions. For optimisation of combinational circuits, new techniques and algorithms based on algebraic techniques are developed which can be used to generate reduced RM expressions to design circuits in RM/DRM domain starting from FPRM/FPDRM, respectively. The outcome for these techniques is expansion in Reed Muller domain with minimal terms. The search space is 3`" Exclusive OR Sum of Product (ESOP)/or Exclusive NOR Product of Sums (ENPOS) expansions. Genetic Algorithms (GAs) are also developed to optimise combinational circuits to find optimal MPRM/MPDRM among 3° different polarities without the need to do exhaustive search. These algorithms are developed for completely and incompletely specified Boolean functions. The experimental results show that GA can find optimum solutions in a short time compared with long time required running exhaustive search in all the benchmarks tested. Multi Objective Genetic Algorithm (MOGA) is developed and implemented to determine the optimal state assignment which results in less area and power dissipation for completely and incompletely specified sequential circuits. The goal is to find the best assignments which reduce the component count and switching activity simultaneously. The experimental results show that saving in components and switching activity are achieved in most of the benchmarks tested compared with recently published research. All algorithms are implemented in C++.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Modeling and Evaluating Energy Performance of Smartphones

With advances in hardware miniaturization and wireless communication technologies even small portable wireless devices have much communication bandwidth and computing power. These devices include smartphones, tablet computers, and personal digital assistants. Users of these devices expect to run software applications that they usually have on their desktop computers as well as the new applications that are being developed for mobile devices. Web browsing, social networking, gaming, online multimedia playing, global positioning system based navigation, and accessing emails are examples of a few popular applications. Mobile versions of thousands of desktop applications are already available in mobile application markets, and consequently, the expected operational time of smartphones is rising rapidly. At the same time, the complexity of these applications is growing in terms of computation and communication needs, and there is a growing demand for energy in smartphones. However, unlike the exponential growth in computing and communication technologies, in terms of speed and packaging density, battery technology has not kept pace with the rapidly growing energy demand of these devices. Therefore, designers are faced with the need to enhance the battery life of smartphones. Knowledge of how energy is used and lost in the system components of the devices is vital to this end. With this view, we focus on modeling and evaluating the energy performance of smartphones in this thesis. We also propose techniques for enhancing the energy efficiency and functionality of smartphones. The detailed contributions of the thesis are as follows: (i) we present a nite state machine based model to estimate the energy cost of an application running on a smartphone, and provide practical approaches to extract model parameters; (ii) the concept of energy cost pro le is introduced to assess the impact of design decisions on energy cost at an early stage of software design; (iii) a generic architecture is proposed and implemented for enhancing the capabilities of smartphones by sharing resources; (iv) we have analyzed the Internet tra c of smartphones to observe the energy saving potentials, and have studied the implications on the existing energy saving techniques; and nally, (v) we have provided a methodology to select user level test cases for performing energy cost evaluation of applications. All of our concepts and proposed methodology have been validated with extensive measurements on a real test bench. Our work contributes to both theoretical understanding of energy e ciency of software applications and practical methodologies for evaluating energy e ciency. In summary, the results of this work can be used by application developers to make implementation level decisions that affect the energy efficiency of software applications on smartphones. In addition, this work leads to the design and implementation of energy e cient smartphones

Computer aided synthesis and optimisation of electronic logic circuits

In this thesis, a variety of algorithms for synthesis and optimisation of combinational and sequential logic circuits are developed. These algorithms could be part of new commercial EGAD package for future VLSI digital designs. The results show that considerable saving in components can be achieved resulting in simpler designs that are smaller, cheaper, consume less power and easier to test.The purpose of generating different sets of coefficients related to Reed Muller (RM) is that they contain different number of terms; therefore the minimum one can be selected to design the circuits with reduced gate count. To widen the search space and achieve better synthesis tools, representations of Mixed Polarity Reed Muller (MPRM), Mixed Polarity Dual Reed Muller (MPDRM), and Pseduo Kronecker Reed Muller (PKRO RM) expansions are investigated. Efficient and fast combinatorial techniques and algorithms are developed for the following:- Bidirectional conversion between MPRM/ MPDRM form and Fixed Polarity Reed Muller forms (FPRM)/Fixed Polarity Dual Reed Muller forms (FPDRM) form respectively. The main advantages for these techniques are their simplicity and suitability for single and multi output Boolean functions.- Computing the coefficients of any polarity related to PKRO_RM class starting from FPRM coefficients or Canonical Sum of Products (CSOP).- Computing the coefficients of any polarity related to MPRM/or MPDRM directly from standard form of CSOP/Canonical Product of sums (CPOS) Boolean functions, respectively. The proposed algorithms are efficient in terms of CPU time and can be used for large functions.For optimisation of combinational circuits, new techniques and algorithms based on algebraic techniques are developed which can be used to generate reduced RM expressions to design circuits in RM/DRM domain starting from FPRM/FPDRM, respectively. The outcome for these techniques is expansion in Reed Muller domain with minimal terms. The search space is 3`" Exclusive OR Sum of Product (ESOP)/or Exclusive NOR Product of Sums (ENPOS) expansions.Genetic Algorithms (GAs) are also developed to optimise combinational circuits to find optimal MPRM/MPDRM among 3° different polarities without the need to do exhaustive search. These algorithms are developed for completely and incompletely specified Boolean functions. The experimental results show that GA can find optimum solutions in a short time compared with long time required running exhaustive search in all the benchmarks tested.Multi Objective Genetic Algorithm (MOGA) is developed and implemented to determine the optimal state assignment which results in less area and power dissipation for completely and incompletely specified sequential circuits. The goal is to find the best assignments which reduce the component count and switching activity simultaneously. The experimental results show that saving in components and switchingactivity are achieved in most of the benchmarks tested compared with recentlypublished research. All algorithms are implemented in C++