Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

On-chip signaling techniques for high-speed Serdes transceivers

The general goal of the VLSI technology is to produce very fast chips with very low power consumption. The technology scaling along with increasing the working frequency had been the perfect solution, which enabled the evolution of electronic devices in the 20th century. However, in deep sub-micron technologies, the on-chip power density limited the continuous increment in frequency, which led to another trend for designing higher performance chips without increasing the working speed. Parallelism was the optimum solution, and the VLSI manufacturers began the era of multi-core chips. These multi-core chips require a full inter-core network for the required communication. These on-chip links were conventionally parallel. However, due to reverse scaling in modern technologies, parallel signaling is becoming a burden due to the very large area of needed interconnects. Also, due to the very high power due to the tremendous number of repeaters, in addition to cross talk issues. As a solution, on-chip serial communication was suggested. It will solve all the previous issues, but it will require very high speed circuits to achieve the same data rates. This thesis presents two full SerDes transceiver designs for on-chip high speed serial communication. Both designs use long lossy on-chip differential interconnects with capacitive termination. The first design uses a 3-level self-timed signaling technique. This signaling technique is totally jitter-insensitive, since both of the data and clock are extracted at the receiver from the same signal. A new encoding and driving technique is designed to enable the transmitter to work at a frequency equal to the data rate, which is half of the frequency of the previous designs, along with achieving the same data rate. Also, this design generates the third voltage level without the need of an external supply. This design is very tolerant to any possible variations, such as PVT variations or the input clock\u27s duty cycle variations. This transceiver is prepared for tape-out in UMC 0.13μm CMOS technology in June 2014. The second design uses a new 3-level signaling technique; the proposed technique uses a frequency of only half the data rate, which totally relaxes the full transceiver design. The new technique is also self-timed enabling the extraction of both the data, and the clock from the same signal. New encoders and decoders are designed, and a new architecture for a 3-level inverter is presented. This transceiver achieves very high data rates. This new design is expected to be taped-out using the GF 65nm CMOS technology in August 2014

Dimming control in visible light communication using RPO-OFDM and concatenated RS-CC

Increasing wireless data traffic is creating pressure on the conventional dwindling radio frequency spectrum. A new and reliable communication medium becomes a necessity. Visible Light Communication (VLC), a subset of optical wireless communication uses the visible light spectrum between 400 and 800 THz as a medium for communication. VLC utilizes the illumination of LED to establish a communication medium. The research focused on achieving a successful VLC communication link at low intensities of light without affecting the speed, accuracy and efficiency of VLC. The achievement of the paper was to devise a method to reduce the LED brightness, reducing energy consumption and most importantly maintain a reliable, efficient and successful VLC communication link at low intensities of LED. The research comprises of a Reverse Polarity Optical-Orthogonal Frequency Division Multiplexing (RPO-OFDM) modulator, a Forward Error Correction (FEC) encoder block that uses concatenated Reed Solomon - Convolutional Coding, a digital PWM dimming control circuit, an RPO-OFDM demodulator and a FEC decoder. The decoding is performed using the Berlekamp-Massey algorithm and the Viterbi algorithm. Extensive research on various modulation schemes, coding and error correction techniques along with various driver circuit design for dimming control in VLC were thoroughly investigated to conclude the best reliable solution for dimming control in VLC

High Performance Optical Transmitter Ffr Next Generation Supercomputing and Data Communication

High speed optical interconnects consuming low power at affordable prices are always a major area of research focus. For the backbone network infrastructure, the need for more bandwidth driven by streaming video and other data intensive applications such as cloud computing has been steadily pushing the link speed to the 40Gb/s and 100Gb/s domain. However, high power consumption, low link density and high cost seriously prevent traditional optical transceiver from being the next generation of optical link technology. For short reach communications, such as interconnects in supercomputers, the issues related to the existing electrical links become a major bottleneck for the next generation of High Performance Computing (HPC). Both applications are seeking for an innovative solution of optical links to tackle those current issues. In order to target the next generation of supercomputers and data communication, we propose to develop a high performance optical transmitter by utilizing CISCO Systems®\u27s proprietary CMOS photonic technology. The research seeks to achieve the following outcomes: 1. Reduction of power consumption due to optical interconnects to less than 5pJ/bit without the need for Ring Resonators or DWDM and less than 300fJ/bit for short distance data bus applications. 2. Enable the increase in performance (computing speed) from Peta-Flop to Exa-Flops without the proportional increase in cost or power consumption that would be prohibitive to next generation system architectures by means of increasing the maximum data transmission rate over a single fiber. 3. Explore advanced modulation schemes such as PAM-16 (Pulse-Amplitude-Modulation with 16 levels) to increase the spectrum efficiency while keeping the same or less power figure. This research will focus on the improvement of both the electrical IC and optical IC for the optical transmitter. An accurate circuit model of the optical device is created to speed up the performance optimization and enable co-simulation of electrical driver. Circuit architectures are chosen to minimize the power consumption without sacrificing the speed and noise immunity. As a result, a silicon photonic based optical transmitter employing 1V supply, featuring 20Gb/s data rate is fabricated. The system consists of an electrical driver in 40nm CMOS and an optical MZI modulator with an RF length of less than 0.5mm in 0.13&mu m SOI CMOS. Two modulation schemes are successfully demonstrated: On-Off Keying (OOK) and Pulse-Amplitude-Modulation-N (PAM-N N=4, 16). Both versions demonstrate signal integrity, interface density, and scalability that fit into the next generation data communication and exa-scale computing. Modulation power at 20Gb/s data rate for OOK and PAM-16 of 4pJ/bit and 0.25pJ/bit are achieved for the first time of an MZI type optical modulator, respectively

AUTOMATIC METER READING USING ZIGBEE

The real-time monitoring of a data is crucial in ensuring the accuracy of the acquired data. It determines whether the device is properly working or in fault. This paper proposed the design and implementation of a ZigBee-based wireless automatic meter reading system. It focuses on the development of a device that is capable of monitoring meter reader remotely. It sends the data hourly or daily using Zigbee as the transmitting medium. The proposed device uses software; XCTU, Arduino Programming Language, Multisim and hardware; Microcontroller, Pulse generating circuit, Zigbee antenna, 16X2 LCD Display to actually demonstrate the result. This device has a good potential in wireless meter reading due to its low-cost, low power consuming, and low data rate. The input is the pulse generated by the pulsating circuit and the output will be shown onto the LCD display and in the XCTU software proving that it transmitted wirelessly. The results successfully shows the data is received as what it is transmitted. If the prototype would be able to be completed within time limit, the author might explore more on using GSM/GPRS module to transfer the data further in term of distance. The report consists of an introduction, problem statement, objectives, literature review and methodology used to solve the problem. It further looks into the obtained results with consistent discussion

Autonomous Scale Car Using Computer Vision and Neural Networks

This report explores the feasibility of creating an autonomous 1:10 scale car capable of racing against RC cars on any indoor track. Custom made and equipped with a livestream sensor display module, the car leverages Artificial Neural Networks (ANN) to produce optimal driving outputs. Manipulating grayscale pixel input from a single, front-facing camera, the car navigates without the use of mapping or localization. Instead, the car relies on extensive training that allows the vehicle to adapt to variable conditions

Electromechanical System Integration for a Powered Upper Extremity Orthosis

Wearable robotics for assistance and rehabilitation are not yet considered commercially mainstream products, and as a result have not yet seen advanced controls systems and interfaces. Consequently, the available technology is mostly adapted from systems used in parallel technologies, rather than custom applications intended for human use. This study concerns itself with the design and development of a custom control system for a 2-degree of freedom powered upper extremity orthosis capable of driving elbow flexion/extension 135º and humeral rotation 95º . The orthosis has been evaluated for use as both a long-term assistive technology device for persons with disabilities, and as a short-term rehabilitative tool for persons recovering injury. The target demographics for such a device vary in age, cognitive ability and physical function, thus requiring several input parameters requiring consideration. This study includes a full evaluation of the potential users of the device, as well as parameter considerations that are required during the design phase. The final control system is capable of driving each DOF independently or simultaneously, for a more realistic and natural coupled-motion, with proportional control by pulse-width modulation. The dual-axis joystick interface wirelessly transmits to the 1.21 pound control pack which houses a custom microcontroller-driven PCB and 1800 milliamp-hour lithium-ion rechargeable battery capable of delivering 4 hours of running time. Upon integration with the 2 DOF orthosis device, a user may complete full range of motion with up to 5 pounds in their hand in less than 7 seconds, providing full functionality to complete acts of daily living, thus improving quality of life

On-board processing satellite network architecture and control study

The market for telecommunications services needs to be segmented into user classes having similar transmission requirements and hence similar network architectures. Use of the following transmission architecture was considered: satellite switched TDMA; TDMA up, TDM down; scanning (hopping) beam TDMA; FDMA up, TDM down; satellite switched MF/TDMA; and switching Hub earth stations with double hop transmission. A candidate network architecture will be selected that: comprises multiple access subnetworks optimized for each user; interconnects the subnetworks by means of a baseband processor; and optimizes the marriage of interconnection and access techniques. An overall network control architecture will be provided that will serve the needs of the baseband and satellite switched RF interconnected subnetworks. The results of the studies shall be used to identify elements of network architecture and control that require the greatest degree of technology development to realize an operational system. This will be specified in terms of: requirements of the enabling technology; difference from the current available technology; and estimate of the development requirements needed to achieve an operational system. The results obtained for each of these tasks are presented

Clock Jitter in Communication Systems

For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces