Analysis and design of a high power millimeter-wave power amplifier in a SiGe BiCMOS technology

Our current society is characterized by an ever increasing need for bandwidth leading towards the exploration of new parts of the electromagnetic spectrum for data transmission. This results in a rising interest and development of millimeter-wave (mm-wave) circuits which hold the promise of short range multi-gigabit wireless transmissions at 60GHz. These relatively new applications are to co-exist with more established mm-wave consumer products including satellite systems in the Ka-band (26.5GHz - 40GHz) allowing e.g.: video broadcasting, voice over IP (VoIP), internet acces to remote areas, ... Both need significant linear power amplification due to the high attenuation typical for this part of the spectrum, however, satellite systems demand a saturated output power which is easily an order of magnitude larger (output powers in excess of 30dBm / 1W). Monolithic microwave integrated circuits (MMICs) employing III-V chip technologies, e.g.: gallium arsenide (GaAs), gallium nitride (GaN), have historically been the preferred choice to implement efficient mm-wave power amplifiers (PA) with a high saturated output power (>30dBm). To further increase the commercial viability of consumer products in this market segment a low manufacturing cost for the power amplifier, together with the possible integration of additional functions, is highly desirable. These features are the strongpoint of silicon based chip technologies like CMOS and SiGe BiCMOS. However, these technologies have a breakdown voltage typically below 2V for nodes capable of millimeter-wave applications while III-V transistors with equivalent frequency performance demonstrate breakdown voltages in excess of 8V. Because of this, output powers of CMOS and SiGe BiCMOS Ka-band power amplifiers rarely exceed 20dBm which poses the main hurdle for using these technologies in satellite communication (SATCOM). To overcome the limited output power of a single amplifying cell in a silicon technology, caused by the low breakdown voltage, multiple power amplifiers cells need to have their output power effectively combined on-chip. This requires the on-chip integration of high-Q passives within a relative small area to realize both the impedance transformation, to create the optimal load impedance for the different amplifier cells, and implement an efficient on-chip power combination network. Compared to III-V technologies this is again a challenge due to the use of a silicon substrate which introduces higher losses. Once a large enough on-chip output power is created, the issue of launching this signal to the outside world remains. Moreover, due to the limited efficiency of mm-wave PAs, the generated on-chip heat will increase when larger output power are required. This means a chipto-board interface with a low thermal resistance and a low loss electrical connection needs to be devised. Proof of the viability of silicon as a serious candidate for the integration of medium and high power Ka-band amplifiers will only be delivered by long term research and the actual creation of such an amplifier. In this context, the initial goal for the presented work is proposed. This consists of the creation of a power amplifier with a saturated output power above 24dBm (preferably 27dBm), a gain larger than 20dB and an efficiency in excess of 10% (preferably 15%). These specifications where conceived with the precondition of using a 250nm SiGe BiCMOS technology (IHP’s SG25H3) with an fT of 110GHz and a collector to emitter breakdown voltage in open base conditions (BVCEO) of 2.3V. The use of this technology is a significant challenge due to the limited speed, rule of thumb is to have at least one fifth of the fT as the operating frequency, which reflects in the attainable power added efficiency (PAE). On the other hand, proving the possible implementation in this “older” technology shows great potential towards the future integration in a fast technology (e.g.: IHP’s SG13G2, ft =300GHz). Next to issues caused by limitations of the chip technology, the proposed specifications allows to identify generic difficulties with high power silicon PA design, e.g.: design of efficient on-chip power combiners, thermal management, single-ended to differential conversion, ... As this work is of an academic nature the intention of this design was to leave the beaten track and explore alternative topologies. This has led to the adoption of a driver stage using translinear loops for biasing and a transformer-type Wilkinson power combiner previously only used in cable television (CATV) applications. Although the power combiner showed 2dB more loss than expected due to higher than expected substrate losses, both topologies show promise for further integration. Furthermore, an in-depth analysis was performed on the output stage which uses positive feedback to increase its gain. The entire design consists of a four-way power combining class AB power amplifier together with test structures of which the performance was verified by means of probing. Due to the previously mentioned higher than expected loss in the on-chip power combiner, the total output power and power added efficiency (PAE) was 2dB lower than expected from simulations. The result is a saturated output power at 32GHz of 24.1dBm with a PAE of 7.2% and a small signal gain of 25dB. This demonstrates the capability of SiGe BiCMOS to implement PA’s for medium-power mm-wave applications. Moreover, to the best of the author’s knowledge, this PA achieves the second highest saturated output power when comparing SiGe BiCMOS PA’s with center frequency in or close to the Ka-band. The 1dB compression point of this amplifier lies at 22.7dBm which is close to saturated output power and results in a low spectral regrowth when compared to commercial GaAs PA’s (compared with 2MBaud 16QAM input signal at 10dB back-off). Many possible improvements to this design remain. The most important would be the re-design of the on-chip power combiner, possibly with a floating ground shield, to reduce the losses and increase the total output power and PAE. Also the porting of the design to a faster chip technology might result in a considerable increase of the output stage efficiency at the cost of needing to combine more amplifier cells. The transition to a faster chip technology would additionally allow to use this design for alternative mm-wave applications like automotive radar at 79GHz andWiGig at 60GHz

A comparison of processing techniques for producing prototype injection moulding inserts.

This project involves the investigation of processing techniques for producing low-cost moulding inserts used in the particulate injection moulding (PIM) process. Prototype moulds were made from both additive and subtractive processes as well as a combination of the two. The general motivation for this was to reduce the entry cost of users when considering PIM. PIM cavity inserts were first made by conventional machining from a polymer block using the pocket NC desktop mill. PIM cavity inserts were also made by fused filament deposition modelling using the Tiertime UP plus 3D printer. The injection moulding trials manifested in surface finish and part removal defects. The feedstock was a titanium metal blend which is brittle in comparison to commodity polymers. That in combination with the mesoscale features, small cross-sections and complex geometries were considered the main problems. For both processing methods, fixes were identified and made to test the theory. These consisted of a blended approach that saw a combination of both the additive and subtractive processes being used. The parts produced from the three processing methods are investigated and their respective merits and issues are discussed

Design Techniques of Highly Integrated Hybrid-Switched-Capacitor-Resonant Power Converters for LED Lighting Applications

The Light-emitting diodes (LEDs) are rapidly emerging as the dominant light source given their high luminous efficacy, long lift span, and thanks to the newly enacted efficiency standards in favor of the more environmentally-friendly LED technology. The LED lighting market is expected to reach USD 105.66 billion by 2025. As such, the lighting industry requires LED drivers, which essentially are power converters, with high efficiency, wide input/output range, low cost, small form factor, and great performance in power factor, and luminance flicker. These requirements raise new challenges beyond the traditional power converter topologies. On the other hand, the development and improvement of new device technologies such as printed thin-film capacitors and integrated high voltage/power devices opens up many new opportunities for mitigating such challenges using innovative circuit design techniques and solutions. Almost all electric products needs certain power delivery, regulation or conversion circuits to meet the optimized operation conditions. Designing a high performance power converter is a real challenge given the market’s increasing requirements on energy efficiency, size, cost, form factor, EMI performance, human health impact, and so on. The design of a LED driver system covers from high voltage AC/DC and DC/DC power converters, to high frequency low voltage digital controllers, to power factor correction (PFC) and EMI filtering techniques, and to safety solutions such as galvanic isolation. In this thesis, we study design challenges and present corresponding solutions to realize highly integrated and high performance LED drivers combining switched-capacitor and resonant converters, applying re-configurable multi-level circuit topology, utilizing sigma delta modulation, and exploring capacitive galvanic isolation. A hybrid switched-capacitor-resonant (HSCR) LED driver based on a stackable switched-capacitor (SC) converter IC rated for 15 to 20 W applications. Bulky transformers have been replaced with a SC ladder to perform high-efficiency voltage step-down conversion; an L-C resonant output network provides almost lossless current regulation and demonstrates the potential of capacitive galvanic isolation. The integrated SC modules can be stacked in the voltage domain to handle a large range of input voltage ranges that largely exceed the voltage limitation of the medium-voltage-rated 120 V silicon technology. The LED driver demonstrates > 91% efficiency over a rectified input DC voltage range from 160 VDC to 180 VDC with two stacked ICs; using a stack of four ICs > 89.6% efficiency is demonstrated over an input range from 320 VDC to 360 VDC . The LED driver can dim its output power to around 10% of the rated power while maintaining >70% efficiency with a PWM controlled clock gating circuit. Next, the design of AC main rectifier and inverter front end with sigma delta modulation is described. The proposed circuits features a pair of sigma delta controlled multilevel converters. The first is a multilevel rectifier responsible for PFC and dimming. The second is a bidirectional multilevel inverter used to cancel AC power ripple from the DC bus. The system also contains an output stage that powers the LEDs with DC and provides for galvanic isolation. Its functional performance indicates that integrated multilevel converters are a viable topology for lighting and other similar applications

Reducing risk in pre-production investigations through undergraduate engineering projects.

This poster is the culmination of final year Bachelor of Engineering Technology (B.Eng.Tech) student projects in 2017 and 2018. The B.Eng.Tech is a level seven qualification that aligns with the Sydney accord for a three-year engineering degree and hence is internationally benchmarked. The enabling mechanism of these projects is the industry connectivity that creates real-world projects and highlights the benefits of the investigation of process at the technologist level. The methodologies we use are basic and transparent, with enough depth of technical knowledge to ensure the industry partners gain from the collaboration process. The process we use minimizes the disconnect between the student and the industry supervisor while maintaining the academic freedom of the student and the commercial sensitivities of the supervisor. The general motivation for this approach is the reduction of the entry cost of the industry to enable consideration of new technologies and thereby reducing risk to core business and shareholder profits. The poster presents several images and interpretive dialogue to explain the positive and negative aspects of the student process

Launching the Grand Challenges for Ocean Conservation

The ten most pressing Grand Challenges in Oceans Conservation were identified at the Oceans Big Think and described in a detailed working document:A Blue Revolution for Oceans: Reengineering Aquaculture for SustainabilityEnding and Recovering from Marine DebrisTransparency and Traceability from Sea to Shore:  Ending OverfishingProtecting Critical Ocean Habitats: New Tools for Marine ProtectionEngineering Ecological Resilience in Near Shore and Coastal AreasReducing the Ecological Footprint of Fishing through Smarter GearArresting the Alien Invasion: Combating Invasive SpeciesCombatting the Effects of Ocean AcidificationEnding Marine Wildlife TraffickingReviving Dead Zones: Combating Ocean Deoxygenation and Nutrient Runof

Innovating Toward Excellence: Education Entrepreneurs and the Transformation of Public Education

Summarizes discussions among education entrepreneurs, funders, policy makers, and experts at a May 2009 summit on innovations in ideas, processes, and products for reform. Includes a case study review of a successful turnaround of a failing school

Challenges and complexities in application of LCA approaches in the case of ICT for a sustainable future

In this work, three of many ICT-specific challenges of LCA are discussed. First, the inconsistency versus uncertainty is reviewed with regard to the meta-technological nature of ICT. As an example, the semiconductor technologies are used to highlight the complexities especially with respect to energy and water consumption. The need for specific representations and metric to separately assess products and technologies is discussed. It is highlighted that applying product-oriented approaches would result in abandoning or disfavoring of new technologies that could otherwise help toward a better world. Second, several believed-untouchable hot spots are highlighted to emphasize on their importance and footprint. The list includes, but not limited to, i) User Computer-Interfaces (UCIs), especially screens and displays, ii) Network-Computer Interlaces (NCIs), such as electronic and optical ports, and iii) electricity power interfaces. In addition, considering cross-regional social and economic impacts, and also taking into account the marketing nature of the need for many ICT's product and services in both forms of hardware and software, the complexity of End of Life (EoL) stage of ICT products, technologies, and services is explored. Finally, the impact of smart management and intelligence, and in general software, in ICT solutions and products is highlighted. In particular, it is observed that, even using the same technology, the significance of software could be highly variable depending on the level of intelligence and awareness deployed. With examples from an interconnected network of data centers managed using Dynamic Voltage and Frequency Scaling (DVFS) technology and smart cooling systems, it is shown that the unadjusted assessments could be highly uncertain, and even inconsistent, in calculating the management component's significance on the ICT impacts.Comment: 10 pages. Preprint/Accepted of a paper submitted to the ICT4S Conferenc

Achieving Effective Innovation Based On TRIZ Technological Evolution

Organised by: Cranfield UniversityThis paper outlines the conception of effective innovation and discusses the method to achieve it. Effective Innovation is constrained on the path of technological evolution so that the corresponding path must be detected before conceptual design of the product. The process of products technological evolution is a technical developing process that the products approach to Ideal Final Result (IFR). During the process, the sustaining innovation and disruptive innovation carry on alternately. By researching and forecasting potential techniques using TRIZ technological evolution theory, the effective innovation can be achieved finally.Mori Seiki – The Machine Tool Compan