Preprototype vapor compression distillation subsystem

A three-person capacity preprototype vapor compression distillation subsystem for recovering potable water from wastewater aboard spacecraft was designed, assembled, and tested. The major components of the subsystem are: (1) a distillation unit which includes a compressor, centrifuge, central shaft, and outer shell; (2) a purge pump; (3) a liquids pump; (4) a post-treat cartridge; (5) a recycle/filter tank; (6) an evaporator high liquid level sensor; and (7) the product water conductivity monitor. A computer based control monitor instrumentation carries out operating mode change sequences, monitors and displays subsystem parameters, maintains intramode controls, and stores and displays fault detection information. The mechanical hardware occupies 0.467 m3, requires 171 W of electrical power, and has a dry weight of 143 kg. The subsystem recovers potable water at a rate of 1.59 kg/hr, which is equivalent to a duty cycle of approximately 30% for a crew of three. The product water has no foul taste or odor. Continued development of the subsystem is recommended for reclaiming water for human consumption as well as for flash evaporator heat rejection, urinal flushing, washing, and other on-board water requirements

Communications techniques and equipment: A compilation

This Compilation is devoted to equipment and techniques in the field of communications. It contains three sections. One section is on telemetry, including articles on radar and antennas. The second section describes techniques and equipment for coding and handling data. The third and final section includes descriptions of amplifiers, receivers, and other communications subsystems

MIDAS, prototype Multivariate Interactive Digital Analysis System for large area earth resources surveys. Volume 1: System description

A third-generation, fast, low cost, multispectral recognition system (MIDAS) able to keep pace with the large quantity and high rates of data acquisition from large regions with present and projected sensots is described. The program can process a complete ERTS frame in forty seconds and provide a color map of sixteen constituent categories in a few minutes. A principle objective of the MIDAS program is to provide a system well interfaced with the human operator and thus to obtain large overall reductions in turn-around time and significant gains in throughput. The hardware and software generated in the overall program is described. The system contains a midi-computer to control the various high speed processing elements in the data path, a preprocessor to condition data, and a classifier which implements an all digital prototype multivariate Gaussian maximum likelihood or a Bayesian decision algorithm. Sufficient software was developed to perform signature extraction, control the preprocessor, compute classifier coefficients, control the classifier operation, operate the color display and printer, and diagnose operation

DFT Architecture with Power-Distribution-Network Consideration for Delay-based Power Gating Test

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability (DFT) logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers trade-off flexibility between test-application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase test quality when considering systematic variations. Through SPICE simulations, we show complete recovery of the test quality lost due to PDNs. The proposed method is robust sustaining 80.3% to 98.6% of the achieved test quality under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on test quality and offers a unified test solution for both ring and grid power gating styles

SoC Test: Trends and Recent Standards

The well-known approaching test cost crisis, where semiconductor test costs begin to approach or exceed manufacturing costs has led test engineers to apply new solutions to the problem of testing System-On-Chip (SoC) designs containing multiple IP (Intellectual Property) cores. While it is not yet possible to apply generic test architectures to an IP core within a SoC, the emergence of a number of similar approaches, and the release of new industry standards, such as IEEE 1500 and IEEE 1450.6, may begin to change this situation. This paper looks at these standards and at some techniques currently used by SoC test engineers. An extensive reference list is included, reflecting the purpose of this publication as a review paper

Power Droop Reduction In Logic BIST By Scan Chain Reordering

Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scan-based Logic BIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time

Synthetic Aperture Radar (SAR) data processing

The available and optimal methods for generating SAR imagery for NASA applications were identified. The SAR image quality and data processing requirements associated with these applications were studied. Mathematical operations and algorithms required to process sensor data into SAR imagery were defined. The architecture of SAR image formation processors was discussed, and technology necessary to implement the SAR data processors used in both general purpose and dedicated imaging systems was addressed

Design project of a low-cost data acquisition system for electromechanical testing of smart materials

This thesis aims to develop a low-cost data acquisition system to record electrical resistance and deformation data in self-sensing smart cement specimens. Subsequently, the developed system must be tested with cyclic load tests, a text file must be generated with the data obtained and said data must be analysed to extract conclusions about the performance of the system and the piezoresistive "smartness" of the materials. The most interesting application of this thesis is to implement the system designed in an intelligent cement for Structural Health Monitoring applications, where a structure can be continuously monitored to detect deformations and possible failures before they happen. For this reason, the research on this thesis’s state of the art has focused on the current applications of smart cement, current SHM systems and research about low-cost solutions. To achieve the thesis goals, fluent communication has been established between the thesis director and the author, both by exchanging emails and face-to-face meetings. In addition, face-to-face sessions have been held in the Resistance of Materials laboratory, such as preparing the test specimens and testing the data acquisition system at different points in the thesis. The results show that the developed system can record electrical resistance and deformation data and generate text files for its processing. The analysis of the obtained data also illustrates the linear relationship between the fractional change in the electrical resistance and the deformation, allowing in this way to characterize the specimens with their gauge factor and thus determine their "smartness”. To sum up, it can be established that this thesis manages to develop a low-cost system for the acquisition of reliable and replicable data and, due to its linear relationship, the cement can be considered "self-sensing" since the application of a load is translated into a change into the electrical resistance, eliminating in this way the need for off-the-shelf strain sensors in SHM systems

Advanced digital SAR processing study

A highly programmable, land based, real time synthetic aperture radar (SAR) processor requiring a processed pixel rate of 2.75 MHz or more in a four look system was designed. Variations in range and azimuth compression, number of looks, range swath, range migration and SR mode were specified. Alternative range and azimuth processing algorithms were examined in conjunction with projected integrated circuit, digital architecture, and software technologies. The advaced digital SAR processor (ADSP) employs an FFT convolver algorithm for both range and azimuth processing in a parallel architecture configuration. Algorithm performace comparisons, design system design, implementation tradeoffs and the results of a supporting survey of integrated circuit and digital architecture technologies are reported. Cost tradeoffs and projections with alternate implementation plans are presented

Index to NASA Tech Briefs, 1975

This index contains abstracts and four indexes--subject, personal author, originating Center, and Tech Brief number--for 1975 Tech Briefs