Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA

High throughput while maintaining low resource is a key issue for elliptic curve cryptography (ECC) hardware implementations in many applications. In this brief, an ECC processor architecture over Galois fields is presented, which achieves the best reported throughput/area performance on field-programmable gate array (FPGA) to date. A novel segmented pipelining digit serial multiplier is developed to speed up ECC point multiplication. To achieve low latency, a new combined algorithm is developed for point addition and point doubling with careful scheduling. A compact and flexible distributed-RAM-based memory unit design is developed to increase speed while keeping area low. Further optimizations were made via timing constraints and logic level modifications at the implementation level. The proposed architecture is implemented on Virtex4 (V4), Virtex5 (V5), and Virtex7 (V7) FPGA technologies and, respectively, achieved throughout/slice figures of 19.65, 65.30, and 64.48 (106/(Seconds × Slices))

High Speed and Low Latency ECC Implementation over GF(2m) on FPGA

In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7)

Low area ECC implementation on FPGA

In this paper, a new compact standalone design of an Elliptic Curve Cryptography (ECC) processor over Galois field GF (2163) is analysed and implemented on FPGA for the three most popular point multiplication algorithms (the basic binary, Montgomery, and Frobenius map). We demonstrate new concurrency in point addition and point doubling together with novel flexible memory and efficient arithmetic units. We investigate area-time and area2 -time performances exploiting a very compact bit/digit serial multiplier. We include a very low cost 8-bit input-output interface that can be embedded with 8-bit processors for low area applications. We compare our results with relevant works on different FPGAs (Virtex (V, Ve, V2, V2p, V4, V5) and Spartan (S3 and S6)). Our Montgomery implementation on V5 shows the best result achieving 0.11 ms for an ECC point multiplication with only 473 slices in area. To our knowledge, the proposed architecture achieves the best area2-time metric performance on FPGA to date