An X-Band low-power and low-phase-noise VCO using bondwire inductor

In this paper a low-power low-phase-noise voltage-controlled-oscillator (VCO) has been designed and, fabricated in 0.25 μm SiGe BiCMOS process. The resonator of the VCO is implemented with on-chip MIM capacitors and a single aluminum bondwire. A tail current filter is realized to suppress flicker noise up-conversion. The measured phase noise is −126.6 dBc/Hz at 1 MHz offset from a 7.8 GHz carrier. The figure of merit (FOM) of the VCO is −192.5 dBc/Hz and the VCO core consumes 4 mA from a 3.3 V power supply. To the best of our knowledge, this is the best FOM and the lowest phase noise for bondwire VCOs in the X-band. This VCO will be used for satellite communications

Research for Pseudo Millimeter Wave Circuit Design with 0.18μm CMOS Technology Node

九州工業大学博士学位論文 学位記番号:工博甲第405号 学位授与年月日:平成27年9月25日第一章：イントロダクション | 第二章：技術的課題 | 第三章：モデリング(ディエンベディング)手法 | 第四章：受動素子の設計とそのモデリング結果 | 第五章：K u - バンドの衛星放送受信機用低雑音ブロックに関する研究 | 第六章：K a - バンド周波数変調連続波変調用レーダに適したVCO の研究 | 第七章：結論九州工業大学平成27年

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Phase noise reduction of a 0.35 μm BiCMOS SiGe 5 GHz Voltage Controlled Oscillator

The research conducted in this dissertation studies the issues regarding the improvement of phase noise performance in a BiCMOS Silicon Germanium (SiGe) cross-coupled differential-pair voltage controlled oscillator (VCO) in a narrowband application as a result of a tail-current shaping technique. With this technique, low-frequency noise components are reduced by increasing the signal amplitude without consuming additional power, and its effect on overall phase noise performance is evaluated. The research investigates effects of the tail-current as a main contributor to phase noise, and also other effects that may influence the phase noise performance like inductor geometry and placement, transistor sizing, and the gain of the oscillator. The hypothesis is verified through design in a standard 0.35 μm BiCMOS process supplied by Austriamicrosystems (AMS). Several VCOs are fabricated on-chip to serve for a comparison and verify that the employment of tail-current shaping does improve phase noise performance. The results are then compared with mathematical models and simulated results, to confirm the hypothesis. Simulation results provided a 3.3 dBc/Hz improvement from -105.3 dBc/Hz to -108.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when employing tail-current shaping. The relatively small increase in VCO phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. Parametric analysis provided an additional 1.8 dBc/Hz performance enhancement in phase noise that can be investigated in future works. The power consumption of the simulated VCO is around 6 mW and 4.1 mW for the measured prototype. The circuitry occupies 2.1 mm2 of die area. CopyrightDissertation (MEng)--University of Pretoria, 2010.Electrical, Electronic and Computer Engineeringunrestricte

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

A Fully Differential Phase-Locked Loop With Reduced Loop Bandwidth Variation

Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop accordingly to meet the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices. Specically this entails meeting stringent noise specications imposed by modern wireless standards, meeting low power consumption budgets to prolong battery lifetimes, operating under reduced supply voltages imposed by modern technology nodes and within the noisy environments of complex system-on-chip (SOC) designs, all in addition to consuming as little silicon area as possible. The ability of the PLL to achieve the above is thus key to its continual progress in enabling wireless technology achieve increasingly powerful products which increasingly benet our daily lives. This thesis furthers the development of PLLs with respect to meeting the challenges imposed upon it by modern wireless technology, in two ways. Firstly, the thesis describes in detail the advantages to be gained through employing a fully dierential PLL. Specically, such PLLs are shown to achieve low noise performance, consume less silicon area than their conventional counterparts whilst consuming similar power, and being better suited to the low supply voltages imposed by continual technology downsizing. Secondly, the thesis proposes a sub-banded VCO architecture which, in addition to satisfying simultaneous requirements for large tuning ranges and low phase noise, achieves signicant reductions in PLL loop bandwidth variation. First and foremost, this improves on the stability of the PLL in addition to improving its dynamic locking behaviour whilst oering further improvements in overall noise performance. Since the proposed sub-banded architecture requires no additional power over a conventional sub-banded architecture, the solution thus remains attractive to the realm of low power design. These two developments combine to form a fully dierential PLL with reduced loop bandwidth variation. As such, the resulting PLL is well suited to meeting the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices, and thus applicable to the continual development of wireless technology in benetting our daily lives

High Speed Integrated Circuits for High Speed Coherent Optical Communications

With the development of (sub) THz transistor technologies, high speed integrated circuits up to sub-THz frequencies are now feasible. These high speed and wide bandwidth ICs can improve the performance of optical components, coherent optical fiber communication, and imaging systems. In current optical systems, electrical ICs are used primarily as driving amplifiers for optical modulators, and in receiver chains including TIAs, AGCs, LPFs, ADCs and DSPs. However, there are numerous potential applications in optics using high speed ICs, and different approaches may be required for more efficient, compact and flexible optical systems.This dissertation will discuss three different approaches for optical components and communication systems using high speed ICs: a homodyne optical phase locked loop (OPLL), a heterodyne OPLL, and a new WDM receiver architecture.The homodyne OPLL receiver is designed for short-link optical communication systems using coherent modulation for high spectral efficiency. The phase-locked coherent receiver can recover the transmitted data without requiring complex back-end digital signal processing to recover the phase of the received optical carrier. The main components of the homodyne OPLL are a photonic IC (PIC), an electrical IC (EIC), and a loop filter. One major challenge in OPLL development is loop bandwidth; this must be of order 1 GHz in order for the loop to adequately track and suppress the phase fluctuations of the locked laser, yet a 1 GHz loop bandwidth demands small (<100 ps) propagation delays if the loop is to be stable. Monolithic integration of the high-speed loop components into one electrical and one photonic IC decreases the total loop delay. We have designed and demonstrated an OPLL with a compact size of 10 × 10 mm2, stably operating with a loop bandwidth of 1.1 GHz, a loop delay of 120 ps, a pull-in time of 0.55 μs and lock time of <10 ns. The coherent receiver can receive 40 Gb/s BPSK data with a bit error rate (BER) of <10-7, and operates up to 35 Gb/s with BER 10-12.The thesis also describes heterodyne OPLLs. These can be used to synthesize optical wavelengths of a broad bandwidth (optical wavelength synthesis) with narrow linewidth and with fast frequency switching. There are many applications of such narrow linewidth optical signal sources, including low phase noise mm-wave and THz-signal sources, wavelength-division-multiplexed optical transmitters, and coherent imaging and sensor systems. The heterodyne OPLL also has the same stability issues (loop delay and sensitivity) as the homodyne OPLL. In the EIC, a single sideband mixer operating using digital design principles (DSSBM) enables precisely controlled sweeping of the frequency of the locked laser, with control of the sign of the frequency offset. The loop's phase and frequency difference detector (PFD) uses digital design techniques to make the OPLL loop parameters only weakly sensitive to optical signal levels or optical or electrical component gains. The heterodyne OPLL operates stably with a loop bandwidth of 550 MHz and loop delay of <200 ps. An initial OPLL design exhibited optical frequency (wavelength) synthesis from -6 GHz to -2 GHz and from 2 GHz to 9 GHz. An improved OPLL reached frequency tuning up to 25 GHz. The homodyne OPLL exhibits -110 dBc/Hz phase noise at 10 MHz offset and -80 dBc/Hz at 5 kHz offset.Finally, the thesis describes a new WDM receiver architecture using broadband electrical ICs. In the proposed WDM receiver, a set of received signals at different optical wavelengths are mixed against a single optical local oscillator. This mixing converts the WDM channels to electrical signals in the receiver photocurrent, with each WDM signal being converted to an RF sub-carrier of different frequency. An electrical IC then separately converts each sub-carrier signal to baseband using single-sideband mixers and quadrature local oscillators. The proposed receiver needs less complex hardware than the arrays of wavelength-sensitive receivers now used for WDM, and can readily adjust to changes in the WDM channel frequencies. The proposed WDM receiver concept was demonstrated through several system experiments. Image rejection of greater than 25 dB, adjacent channel suppression of greater than 20 dB, operation with gridless channels, and six-channel data reception at a total 15 Gb/s (2.5 Gb/s BPSK × 6-channels) were demonstrated