6 research outputs found
Audiovisual preservation strategies, data models and value-chains
This is a report on preservation strategies, models and value-chains for digital file-based audiovisual content. The report includes: (a)current and emerging value-chains and business-models for audiovisual preservation;(b) a comparison of preservation strategies for audiovisual content including their strengths and weaknesses, and(c) a review of current preservation metadata models, and requirements for extension to support audiovisual files
Performance and Energy Consumption Characterization and Modeling of Video Decoding on Multi-core Heterogenous SoC and their Applications
To meet the increasing complexity of mobile multimedia applications, the System on Chip (SoC) equipping modern mobile devices integrate powerful heterogeneous processing elements among which General Purpose Processors (GPP), Digital Signal Processors (DSP), hardware accelerator are the most common ones.Due to the ever-growing gap between battery lifetime and hardware/software complexity in addition to application computing power needs, the energy saving issue becomes crucial in the design of such systems. In this context, we propose a study aiming to enhance the understanding of the energy consumption behavior of video decoding on these kinds of systems. Accordingly, an end-to-end methodology for characterizing and modeling the performance and the energy consumption of video decoding on GPP and DSP is proposed. The characterization step is based on an exhaustive experimental methodology for evaluating, at different abstraction levels, the performance and the energy consumption of video decoding. It was achieved on embedded platforms on which were executed a wide range of video decoding configurations. This step highlighted the importance to consider different parameters which may pertain to different abstraction levels in evaluating the overall energy efficiency of a given system. The measurements obtained in this step were used to build empirically performance and energy models for video decoding on both GPP and DSP. The proposed models gave very accurate estimation (R 2 = 97%) of both the performance and the energy consumption of video decoding in terms of a rich set of parameters including the video quality and the processor frequency. Moreover, based on a multi-level characterization and sub-model decomposition approaches, we show how the developed models, unlike classic empirical models, are easily and rapidly generalizable to other platforms.Some possible applications using the developed models, in the context of adaptive video decoding, were proposed. In general, it consists to use the capability of the proposed performance model to predict the decoding time of a given video quality in dimensioning/scheduling the processing resources. Due to the increasing demand on High Definition (HD), the characterization methodology was extended to consider HD video decoding on both parallel multi-cores and hardware video accelerator. This part highlighted the potential of parallelism video decoding to increase the energy efficiency of video decoding and point out some open issues in this domain.Pour rĂ©pondre Ă la complexitĂ© croissante des applications multimĂ©dia mobiles, les systĂšmes sur puce Ă©quipant les appareils mobiles modernes intĂšgrent des unitĂ©s de calcul puissantes et hĂ©tĂ©rogĂšne. Parmi ces units de calcul, on peut trouver des processeurs Ă usage gĂ©nĂ©ral, des processeur de traitement de signal et des accĂ©lĂ©rateurs matĂ©riels. En raison de lâĂ©cart toujours croissant entre la durĂ©e de vie des batteries et la demande de plus en plus importante en puissance de calcul, lâĂ©conomie dâĂ©nergie devient un enjeu crucial dans la conception des systĂšmes mobiles. Cette problĂ©matique est accentuĂ©e par lâaugmentation de la complexitĂ© des logiciels et architectures matĂ©riels utilisĂ©s. Dans ce contexte, nous proposons une Ă©tude visant Ă amĂ©liorer la comprĂ©hension des considĂ©rations Ă©nergĂ©tiques du dĂ©codage vidĂ©o sur ce genre de systĂšmes. Nous proposerons ainsi une mĂ©thodologie pour la caractĂ©risation et la modĂ©lisation des performances et de la consommation dâĂ©nergie du dĂ©codage vidĂ©o, aussi bien sur des processeurs Ă usage gĂ©nĂ©ral de type ARM que sur un processeurde traitement de signal. LâĂ©tape de caractĂ©risation est basĂ©e sur une mĂ©thodologie expĂ©rimentale pour Ă©valuer de façon exhaustive et Ă diffĂ©rents niveaux dâabstraction, les performances et la consommation dâĂ©nergie du dĂ©codage vidĂ©o. Cette caractĂ©risation a Ă©tĂ© rĂ©alisĂ©e sur des plates-formes embarquĂ©es sur lesquels ont Ă©tĂ© exĂ©cutĂ©s un large Ă©ventail de configurations du dĂ©codage vidĂ©o. Cette Ă©tape a soulignĂ© lâimportance dâexaminer diffĂ©rents paramĂštres qui peuvent se rapporter Ă diffĂ©rents niveaux dâabstraction dans lâĂ©valuation de lâefficacitĂ© Ă©nergĂ©tique globale dâun systĂšme donnĂ©. Les mesures obtenues dans cette Ă©tape ont Ă©tĂ© utilisĂ©es pour construire empiriquement des modĂšles de performance et de consommation dâĂ©nergie pour le dĂ©codage vidĂ©o Ă la fois sur des processeurs Ă usage gĂ©nĂ©ral type ARM et sur un processeur de traitement de signal. Les modĂšles proposĂ©s peuvent estimer avec une grande prĂ©cision (R 2 = 97%) la performance et la consommation dâĂ©nergie de dĂ©codage vidĂ©o en fonction dâun nombre de paramĂštres comprenant la qualitĂ© de la vidĂ©o et la frĂ©quence du processeur. En plus, en se basant sur une caractĂ©risation multi-niveaux et une approches de modĂ©lisation par dĂ©composition en sous-modĂšles, nous montrons comment les modĂšles dĂ©veloppĂ©s, contrairement aux modĂšles empiriques classiques, sont facilement et rapidement gĂ©nĂ©ralisables Ă dâautres plates-formes. Nous proposerons Ă©galement certaines applications possibles des modĂšles dĂ©veloppĂ©s, dans le cadre du dĂ©codage vidĂ©o adaptatif. En gĂ©nĂ©ral, cela consiste Ă exploiter la capacitĂ© du modĂšle de performance proposĂ© pour prĂ©dire le temps de dĂ©codage dâune qualitĂ© vidĂ©o donnĂ©e afin de mieux dimensionner les ressources de calculs dans un but de rĂ©duire leur consommationdâĂ©nergie
Improving Programming Support for Hardware Accelerators Through Automata Processing Abstractions
The adoption of hardware accelerators, such as Field-Programmable Gate Arrays,
into general-purpose computation pipelines continues to rise, driven by recent
trends in data collection and analysis as well as pressure from challenging
physical design constraints in hardware. The architectural designs of many of
these accelerators stand in stark contrast to the traditional von Neumann model
of CPUs. Consequently, existing programming languages, maintenance tools, and
techniques are not directly applicable to these devices, meaning that additional
architectural knowledge is required for effective programming and configuration.
Current programming models and techniques are akin to assembly-level programming
on a CPU, thus placing significant burden on developers tasked with using these
architectures. Because programming is currently performed at such low levels of
abstraction, the software development process is tedious and challenging and
hinders the adoption of hardware accelerators.
This dissertation explores the thesis that theoretical finite automata provide a
suitable abstraction for bridging the gap between high-level programming models
and maintenance tools familiar to developers and the low-level hardware
representations that enable high-performance execution on hardware accelerators.
We adopt a principled hardware/software co-design methodology to develop a
programming model providing the key properties that we observe are necessary for success,
namely performance and scalability, ease of use, expressive power, and legacy
support.
First, we develop a framework that allows developers to port existing, legacy
code to run on hardware accelerators by leveraging automata learning algorithms
in a novel composition with software verification, string solvers, and
high-performance automata architectures. Next, we design a domain-specific
programming language to aid programmers writing pattern-searching algorithms and
develop compilation algorithms to produce finite automata, which supports
efficient execution on a wide variety of processing architectures. Then, we
develop an interactive debugger for our new language, which allows developers to
accurately identify the locations of bugs in software while maintaining support
for high-throughput data processing. Finally, we develop two new
automata-derived accelerator architectures to support additional applications,
including the detection of security attacks and the parsing of recursive and
tree-structured data. Using empirical studies, logical reasoning, and
statistical analyses, we demonstrate that our prototype artifacts scale to
real-world applications, maintain manageable overheads, and support developers'
use of hardware accelerators. Collectively, the research efforts detailed in
this dissertation help ease the adoption and use of hardware accelerators for
data analysis applications, while supporting high-performance computation.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/155224/1/angstadt_1.pd
Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis
As the density of field-programmable gate arrays continues to increase, the size of configuration bitstreams grows accordingly. Compression techniques can reduce memory size and save external memory bandwidth. To accelerate the configuration process and reduce the software startup time, four open-source lossless compression decoders developed using high-level synthesis techniques are presented. Moreover, in order to balance the objectives of compression ratio, decompression throughput, and hardware resource overhead, various improvements and optimizations are proposed. Full bitstreams and software binaries have been collected as a benchmark, and 33 partial bitstreams have also been developed and integrated into the benchmark. Evaluations of the synthesizable compression decoders are demonstrated on a Xilinx ZC706 board, showing higher decompression throughput than those of the existing lossless compression decoders using our benchmark. The proposed decoders can reduce software startup time by up to 31.23% in embedded systems and 69.83% reduction of reconfiguration time for partial reconfigurable systems
Proceedings of the 19th Sound and Music Computing Conference
Proceedings of the 19th Sound and Music Computing Conference - June 5-12, 2022 - Saint-Ătienne (France).
https://smc22.grame.f