400 research outputs found
Logic synthesis and testing techniques for switching nano-crossbar arrays
Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of â\u80\u9cEmerging Computing Modelsâ\u80\u9d or â\u80\u9cComputational Nanoelectronicsâ\u80\u9d, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS
Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects
With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the photolithography. Various reconfigurable architectures have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high-density systems consisting of nanometer-scale elements are likely to have many imperfections and variations; thus, defect-tolerance is considered as one of the most exigent challenges. In this paper, we evaluate three different logic mapping algorithms with defect avoidance to circumvent clustered defective crosspoints in nanowire reconfigurable crossbar architectures. The effectiveness of inherited redundancy and configurability utilization is demonstrated through extensive parametric simulations
Computing with nano-crossbar arrays: Logic synthesis and fault tolerance
Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and can be fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, our project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. First two work packages of the project are presented in this paper. These packages are on logic synthesis that aims to implement Boolean functions with nano-crossbar arrays with area optimization, and fault tolerance that aims to provide a full methodology in the presence of high fault densities and extreme parametric variations in nano-crossbar architectures
Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance
This is a conference paper.Nano-crossbar arrays have emerged as a strong
candidate technology to replace CMOS in near future. They
are regular and dense structures, and can be fabricated such
that each crosspoint can be used as a conventional electronic
component such as a diode, a FET, or a switch. This is a
unique opportunity that allows us to integrate well developed
conventional circuit design techniques into nano-crossbar arrays.
Motivated by this, our project aims to develop a complete synthesis and performance optimization methodology for switching
nano-crossbar arrays that leads to the design and construction
of an emerging nanocomputer. First two work packages of the
project are presented in this paper. These packages are on logic
synthesis that aims to implement Boolean functions with nanocrossbar arrays with area optimization, and fault tolerance that
aims to provide a full methodology in the presence of high fault
densities and extreme parametric variations in nano-crossbar
architectures.This project has received funding from the European Union's H2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 691178
Integrated Synthesis Methodology for Crossbar Arrays
Nano-crossbar arrays have emerged as area and power efficient
structures with an aim of achieving high performance computing
beyond the limits of current CMOS. Due to the stochastic nature
of nano-fabrication, nano arrays show different properties both
in structural and physical device levels compared to conventional
technologies. Mentioned factors introduce random characteristics
that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic
technology preference for switching elements, defect or fault rates
of the given nano switching array and the variation values as well
as their effects on performance metrics including power, delay, and
area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization
algorithms for each step of the process.This work is part of a project that has received funding from the
European Union’s H2020 research and innovation programme under the
Marie Skłodowska-Curie grant agreement No 691178, and supported by the
TUBITAK-Career project #113E76
Defect-tolerance and testing for configurable nano-crossbars
Moore\u27s Law speculated a trend in computation technology in terms of number of transistors per unit area that would double roughly every two years. Even after 40 years of this prediction, current technologies have been following it successfully. There are however, certain physical limitations of current CMOS that would result in fundamental obstructions to continuation of Moore\u27s Law. Although there is a debate amongst experts on how much time it would take for this to happen, it is certain that some entirely new paradigms for semiconductor electronics would be needed to replace CMOS and to delay the end of Moore\u27s Law. Silicon nanowires (SiNW) and Carbon nanotubes (CNT) possess significant promise to replace current CMOS --Abstract, page iv
Neuro-memristive Circuits for Edge Computing: A review
The volume, veracity, variability, and velocity of data produced from the
ever-increasing network of sensors connected to Internet pose challenges for
power management, scalability, and sustainability of cloud computing
infrastructure. Increasing the data processing capability of edge computing
devices at lower power requirements can reduce several overheads for cloud
computing solutions. This paper provides the review of neuromorphic
CMOS-memristive architectures that can be integrated into edge computing
devices. We discuss why the neuromorphic architectures are useful for edge
devices and show the advantages, drawbacks and open problems in the field of
neuro-memristive circuits for edge computing
Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches
Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048 x 2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 10^11 b/cm^2
- …