9 research outputs found

    PROTOTYPING THE SIMULATION OF A GATE LEVEL LOGIC APPLICATION PROGRAM INTERFACE (API) ON AN EXPLICIT-MULTI-THREADED (XMT) COMPUTER

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    Explicit-multi-threading (XMT) is a parallel programming approach for exploiting on-chip parallelism. Its fine-grained SPMD programming model is suitable for many computing intensive applications. In this paper, we present a parallel gate level logic simulation algorithm and study its implementation on an XMT processor. The test results show that hundreds-fold speedup can be achieved

    An efficient graph representation for arithmetic circuit verification

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    Mapping switch-level simulation onto gate-level hardware accelerators

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    In this paper, we present a framework for performing switch-level simulation on hardware accelerators

    Formal verification of an ARM processor

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    *PHDD: an efficient graph representation for floating point circuit verification

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    A Methodology for Hardware Verification Based on Logic Simulation.

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    Logic Simulation On Massively Parallel Architectures

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