Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics

A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the natural visual pathway which renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 /spl mu/m CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5/spl times/10/sup 6/ transistors, most of them operating in analog mode) are presented in this paper.Comisión Interministerial de Ciencia y Tecnología TIC1999-082

Programmable retinal dynamics in a CMOS mixed-signal array processor chip

The low-level image processing that takes place in the retina is intended to compress the relevant visual information to a manageable size. The behavior of the external layers of the biological retina has been successfully modelled by a Cellular Neural Network, whose evolution can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of the focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. For these reasons, a programmable array processor prototype chip has been designed and fabricated in a standard 0.5μm CMOS technology. The integrated system consists of a network of two coupled layers, containing 32 × 32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnections weights. Propagative, active wave phenomena and retina-like effects can be observed in this chip. Design challenges, trade-offs, the buildings blocks and some test results are presented in this paper.Office of Naval Research (USA) N00014-00-10429European Community IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

Fiber optic voice/data network

An asynchronous, high-speed, fiber optic local area network originally developed for tactical environments with additional benefits for other environments such as spacecraft, and the like. The network supports ordinary data packet traffic simultaneously with synchronous T1 voice traffic over a common token ring channel; however, the techniques and apparatus of this invention can be applied to any deterministic class of packet data networks, including multitier backbones, that must transport stream data (e.g., video, SAR, sensors) as well as data. A voice interface module parses, buffers, and resynchronizes the voice data to the packet network employing elastic buffers on both the sending and receiving ends. Voice call setup and switching functions are performed external to the network with ordinary PABX equipment. Clock information is passed across network boundaries in a token passing ring by preceeding the token with an idle period of non-transmission which allows the token to be used to re-establish a clock synchronized to the data. Provision is made to monitor and compensate the elastic receiving buffers so as to prevent them from overflowing or going empty

Speeding up qubit control with bipolar single-flux-quantum pulse sequences

The development of quantum computers based on superconductors requires the improvement of the qubit state control approach aimed at the increase of the hardware energy efficiency. A promising solution to this problem is the use of superconducting digital circuits operating with single-flux-quantum (SFQ) pulses, moving the qubit control system into the cold chamber. However, the qubit gate time under SFQ control is still longer than under conventional microwave driving. Here we introduce the bipolar SFQ pulse control based on ternary pulse sequences. We also develop a robust optimization algorithm for finding a sequence structure that minimizes the leakage of the transmon qubit state from the computational subspace. We show that the appropriate sequence can be found for arbitrary system parameters from the practical range. The proposed bipolar SFQ control reduces a single qubit gate time by halve compared to nowadays unipolar SFQ technique, while maintaining the gate fidelity over 99.99%.Comment: 14 pages, 4 figure

Hardware and Methods for Scaling Up Quantum Information Experiments

Quantum computation promises to solve presently intractable problems, with hopes of yielding solutions to pressing issues to society. Despite this, current machines are limited to tens of qubits. The field is in a state of continuous scaling, with groups around the world working on all aspects of this problem. The work of this thesis aims to contribute to this effort. It is motivated by the goal of increasing both the speed and bandwidth of experiments conducted within our laboratory. Low-loss radio-frequency multiplexers were characterised at cryogenic temperatures, with some shown to operate at below 7mK. The Analog Devices ADG904 was one of these, and its insertion loss was measured at <0.5dB up to 2GHz. Their heat load was measured, and it was found that a switching speed of 10 MHz with an RF signal power of -30dB dissipates 43uW. Installing these switches yields a benefit over installing extra cabling in our cryostat for a switching speed of up to 2MHz and RF power of -30dBm. A switch matrix was prototyped for cryogenic operation, enabling re-routing of wiring inside a cryostat with a minimally increased thermal load. This could be used to significantly increase the scale of high frequency experiments. This switch has also been embedded within a calibration routine, facilitating measurement of a specific feature of interest at millikelvin temperatures. As the field of quantum engineering scales, such measurements will be crucial to close the loop, providing feedback to fabrication and semiconductor growth efforts. Finally, a rapid-turnaround test rig has been developed which has 32 high frequency and 100 DC lines, enabling tests of significant scale in liquid helium. This reduces the time per experiment at 4.2 K to hours rather than days, enabling tests such as thermal cycling, as well as the evaluation of on-chip structures or active electronics and classical computing hardware; which are all necessary elements of any solid state quantum computing architecture

Exploiting Properties of CMP Cache Traffic in Designing Hybrid Packet/Circuit Switched NoCs

Chip multiprocessors with few to tens of processing cores are already commercially available. Increased scaling of technology is making it feasible to integrate even more cores on a single chip. Providing the cores with fast access to data is vital to overall system performance. When a core requires access to a piece of data, the core's private cache memory is searched first. If a miss occurs, the data is looked up in the next level(s) of the memory hierarchy, where often one or more levels of cache are shared between two or more cores. Communication between the cores and the slices of the on-chip shared cache is carried through the network-on-chip(NoC). Interestingly, the cache and NoC mutually affect the operation of each other; communication over the NoC affects the access latency of cache data, while the cache organization generates the coherence and data messages, thus affecting the communication patterns and latency over the NoC. This thesis considers hybrid packet/circuit switched NoCs, i.e., packet switched NoCs enhanced with the ability to configure circuits. The communication and performance benefit that come from using circuits is predicated on amortizing the time cost incurred for configuring the circuits. To address this challenge, NoC designs are proposed that take advantage of properties of the cache traffic, namely temporal locality and predictability, to amortize or hide the circuit configuration time cost. First, a coarse-grained circuit configuration policy is proposed that exploits the temporal locality in the cache traffic to periodically configure circuits for the heavily communicating nodes. This allows the design of a locality-aware cache that promotes temporal communication locality through data placement, while designing suitable data replacement and migration policies. Next, a fine-grained configuration policy, called Déjà Vu switching, is proposed for leveraging predictability of data messages by initiating a circuit configuration as soon as a cache hit is detected and before the data becomes available. Its benefit is demonstrated for saving interconnect energy in multi-plane NoCs. Finally, a more proactive configuration policy is proposed for fast caches, where circuit reservations are initiated by request messages, which can greatly improve communication latency and system performance

Comparison of power consumption in pipelined implementations of the BLAKE3 cipher in FPGA devices

This article analyzes the dynamic power losses generated by various hardware implementations of the BLAKE3 hash function. Estimations of the parameters were based on the results of post-route simulations of designs implemented in Xilinx Spartan-7 FPGAs. The algorithm was tested in various hardware organizations: based on a standard iterative architecture with one round instance in the programmable array, various derived versions with pipeline processing were elaborated, which ultimately led to a set of 6 architectural variants of the cipher, from the iterative case (without pipeline) to one with maximum of 6 pipeline stages. Moreover, the results obtained for the iterative architecture were compared with analogous implementations of the BLAKE2 (direct predecessor) and Keccak (the foundation of the current SHA-3 standard) algorithms. This case study illustrates the differences (or lack thereof) in the power requirements of these three hash functions when they are implemented on an FPGA platform, and illustrate the significant savings that can be achieved by introducing pipeline to the processing of the BLAKE round