Comparing the Efficiency of IP and ATM Telephony

Circuit switching, suited to providing real-time services due to the low and fixed switching delay, is not cost effective for building integrated services networks bursty data traffic because it is based on static allocation of resources which is not efficient with bursty data traffic. Moreover, since current circuit switching technologies handle flows at rates which are integer multiples of 64 kb/s, low bit rate voice encoding cannot be taken advantage of without aggregating multiple phone calls on a single channel. This work explores the real-time efficiency of IP telephony, i.e. the volume of voice traffic with deterministically guaranteed quality related to the amount of network resources used. IP and ATM are taken into consideration as packet switching technology for carrying compressed voice and it is compared to circuit switching carrying PCM (64 Kb/s) encoded voice. ADPCM32 is the voice encoding scheme used throughout most of the paper. The impact of several network parameters, among which the number of hops traversed by a call, on the real-time efficiency is studie

Title of Dissertation: Supporting Distributed Multimedia Applications on ATM Networks

ATM offers a number of features, such as high-bandwidth, and provision for per-connection quality of service guarantees, making it particularly attractive to multimedia applications. Unfortunately, the bandwidth available at ATM's data-link layer is not visible to the applications due to operating system (OS) bottlenecks at the host-network interface. Similarly, the promise of per-connection service guarantees is still elusive due to the lack of appropriate traffic control mechanisms. In this dissertation, we investigate both of these problems, taking multimedia applications as examples. The OS bottlenecks are not limited to the network interfaces, but affect the performance of the entire I/O subsystem. We propose to alleviate OS's I/O bottleneck by according more autonomy to I/O devices and by using a connection oriented framework for I/O transfers. We present experimental results on a video conferencing testbed demonstrating the tremendous performance impact of the proposed I/O architecture on networked multimedia applications. To address the problem of quality of service support in ATM networks, we propose a simple cell scheduling mechanism, named carry-over round robin (CORR). Using analytical techniques, we analyze the delay performance of CORR scheduling. Besides providing guarantees on delay, CORR is also fair in distributing the excess bandwidth. We show that albeit its simplicity, CORR is very competitive with other more complex schemes both in terms of delay performance and fairness. (Also cross-referenced as UMIACS-TR-95-88

Design of traffic shaper / scheduler for packet switches and DiffServ networks : algorithms and architectures

The convergence of communications, information, commerce and computing are creating a significant demand and opportunity for multimedia and multi-class communication services. In such environments, controlling the network behavior and guaranteeing the user\u27s quality of service is required. A flexible hierarchical sorting architecture which can function either as a traffic shaper or a scheduler according to the requirement of the traffic load is presented to meet the requirement. The core structure can be implemented as a hierarchical traffic shaper which can support a large number of connections with a wide variety of rates and burstiness without the loss of the granularity in cells\u27 conforming departure time. The hierarchical traffic shaper can implement the exact sorting scheme with a substantial reduced memory size by using two stages of timing queues, and with substantial reduction in complexity, without introducing any sorting inaccuracy. By setting a suitable threshold to the length of the departure queue and using a lookahead algorithm, the core structure can be converted to a hierarchical rateadaptive scheduler. Based on the traffic load, it can work as an exact sorting traffic shaper or a Generic Cell Rate Algorithm (GCRA) scheduler. Such a rate-adaptive scheduler can reduce the Cell Transfer Delay and the Maximum Memory Occupancy greatly while keeping the fairness in the bandwidth assignment which is the inherent characteristic of GCRA. By introducing a best-effort queue to accommodate besteffort traffic, the hierarchical sorting architecture can be changed to a near workconserving scheduler. It assigns remaining bandwidth to the best-effort traffic so that it improves the utilization, of the outlink while it guarantees the quality of service requirements of those services which require quality of service guarantees. The inherent flexibility of the hierarchical sorting architecture combined with intelligent algorithms determines its multiple functions. Its implementation not only can manage buffer and bandwidth resources effectively, but also does not require no more than off-the-shelf hardware technology. The correlation of the extra shaping delay and the rate of the connections is revealed, and an improved fair traffic shaping algorithm, Departure Event Driven plus Completing Service Time Resorting algorithm, is presented. The proposed algorithm introduces a resorting process into Departure Event Driven Traffic Shaping Algorithm to resolve the contention of multiple cells which are all eligible for transmission in the traffic shaper. By using the resorting process based on each connection\u27s rate, better fairness and flexibility in the bandwidth assignment for connections with wide range of rates can be given. A Dual Level Leaky Bucket Traffic Shaper(DLLBTS) architecture is proposed to be implemented at the edge nodes of Differentiated Services Networks in order to facilitate the quality of service management process. The proposed architecture can guarantee not only the class-based Service Level Agreement, but also the fair resource sharing among flows belonging to the same class. A simplified DLLBTS architecture is also given, which can achieve the goals of DLLBTS while maintain a very low implementation complexity so that it can be implemented with the current VLSI technology. In summary, the shaping and scheduling algorithms in the high speed packet switches and DiffServ networks are studied, and the intelligent implementation schemes are proposed for them

Performance Management in ATM Networks

ATM is representative of the connection-oriented resource provisioning classof protocols. The ATM network is expected to provide end-to-end QoS guaranteesto connections in the form of bounds on delays, errors and/or losses. Performancemanagement involves measurement of QoS parameters, and application of controlmeasures (if required) to improve the QoS provided to connections, or to improvethe resource utilization at switches. QoS provisioning is very important for realtimeconnections in which losses are irrecoverable and delays cause interruptionsin service. QoS of connections on a node is a direct function of the queueing andscheduling on the switch. Most scheduling architectures provide static allocationof resources (scheduling priority, maximum buffer) at connection setup time. Endto-end bounds are obtainable for some schedulers, however these are precluded forheterogeneously composed networks. The resource allocation does not adapt to theQoS provided on connections in real time. In addition, mechanisms to measurethe QoS of a connection in real-time are scarce.In this thesis, a novel framework for performance management is proposed. Itprovides QoS guarantees to real time connections. It comprises of in-service QoSmonitoring mechanisms, a hierarchical scheduling algorithm based on dynamicpriorities that are adaptive to measurements, and methods to tune the schedulers atindividual nodes based on the end-to-end measurements. Also, a novel scheduler isintroduced for scheduling maximum delay sensitive traffic. The worst case analysisfor the leaky bucket constrained traffic arrivals is presented for this scheduler. Thisscheduler is also implemented on a switch and its practical aspects are analyzed.In order to understand the implementability of complex scheduling mechanisms,a comprehensive survey of the state-of-the-art technology used in the industry isperformed. The thesis also introduces a method of measuring the one-way delayand jitter in a connection using in-service monitoring by special cells